Display device, driving method of display device, and electronic appliance

ABSTRACT

A semiconductor device including a plurality of pixels over a substrate and a display medium including an electronic ink over the substrate, in which at least one pixel of the plurality of pixels comprises first and second subpixels each of which comprises a transistor that comprises an oxide semiconductor including indium, and in which one image of at least one of the plurality of pixels is displayed by a plurality of signals, is provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device and a driving methodthereof, particularly relates to a display device to which an area grayscale method is applied and a driving method thereof.

2. Description of the Related Art

In recent years, a so-called self-light emitting display device of whichpixel is formed using a light emitting element such as a light emittingdiode (LED) has attracted attention. As a light emitting element usedfor such a self-light emitting display device, an organic light emittingdiode (also referred to as an OLED (Organic Light Emitting Diode), anorganic EL element, an electroluminescence (EL) element, or the like)has attracted attention, and has been used for an EL display and thelike. Since a light emitting element such as an OLED is a self-lightemitting type, it has advantages of high visibility of pixels, nobacklight required, high response speed, and the like over a liquidcrystal display. Luminance of a light emitting element is controlled bya value of a current flowing through the light emitting element.

As a driving method for controlling a light emitting gray scale of sucha display device, there are a digital gray scale method and an analoggray scale method. In the digital gray scale method, a light emittingelement is turned on/off by digital control to express a gray scale. Onthe other hand, the analog gray scale method includes a method forcontrolling luminance of a light emitting element by an analog mannerand a method for controlling a light emitting period of a light emittingelement by an analog manner.

In a case of the digital gray scale method, there are only two states: alight emitting state and a non-light emitting state. Therefore, only twogray scales can be expressed if nothing is done. Accordingly, anothermethod is used in combination to realize multiple gray scales. An areagray scale method or a time gray scale method is often used as themethod for multiple gray scales.

The area gray scale method is a method for expressing a gray scale bycontrolling the area of a lighting portion. That is, a gray scale isexpressed by dividing one pixel into a plurality of subpixels andcontrolling the number or the area of lighting subpixels (e.g., seeReference 1: Japanese Published Patent Application No. H11-73158 andReference 2: Japanese Published Patent Application No. 2001-125526). Inthe area gray scale method, the number of the subpixels cannot beincreased; therefore, it is difficult to realize high definition andmultiple gray scales. This is given as a disadvantage of the area grayscale method.

The time gray scale method is a method for expressing a gray scale bycontrolling the length of a light emitting period or the frequency oflight emission. That is, one frame is divided into a plurality ofsubframes, each subframe is weighted with respect to the frequency oflight emission, the light emitting period, or the like, and then thetotal weight (the sum of the frequency of light emission or the sum ofthe light emitting period) is differentiated for each gray scale,thereby expressing a gray scale. It is known that display failure calleda pseudo contour (or a false contour) occurs when such a time gray scalemethod is used, and measures against the failure are considered (e.g.,see Reference 3: Japanese Patent No. 2903984, Reference 4: JapanesePatent No. 3075335, Reference 5: Japanese Patent No. 2639311, Reference6: Japanese Patent No. 3322809, Reference 7: Japanese Published PatentApplication No. H10-307561, Reference 8: Japanese Patent No. 3585369,and Reference 9: Japanese Patent No. 3489884).

However, even though various methods for reducing a pseudo contour havebeen suggested, an effect of reducing a pseudo contour has not beensufficiently obtained.

For example, FIGS. 1A and 1B in Reference 4 are referred to, and it isassumed that a gray scale level of 127 is expressed in a pixel A and agray scale level of 128 is expressed in a pixel B next to the pixel A. Alighting or non-lighting state in each subframe of this case is shown inFIGS. 80A and 80B.

Here, how to interpret FIGS. 80A and 80B is described. FIGS. 80A and 80Bare diagrams showing a lighting or non-lighting state of the pixels inone frame. The horizontal direction of FIGS. 80A and 80B indicates time,and the vertical direction thereof indicates each position of thepixels. The length of the horizontal direction of a square in FIGS. 80Aand 80B indicates a relative length of a lighting period in eachsubframe. The area of each square in FIGS. 80A and 80B indicatesbrightness of the pixel in each subframe.

For example, FIG. 80A shows a case where only the pixel A or the pixel Bis seen without moving the eyes. A pseudo contour does not occur in thiscase. This is because the eyes sense the brightness in accordance withthe sum of the brightness of a place where a line of sight passes. Thus,the eyes sense the gray scale level of the pixel A to be 127(=1+2+4+8+16+32+32+32), and the eyes sense the gray scale level of thepixel B to be 128 (=32+32+32+32). That is, the eyes sense an accurategray scale.

On the other hand, FIG. 80B shows a case where a line of sight is movedfrom the pixel A to the pixel B or from the pixel B to the pixel A. Inthis case, the gray scale level is sometimes perceived as 96(=32+32+32), and the gray scale level is sometimes perceived as 159(=1+2+4+8+16+32+32+32+32) depending on a movement of the line of sight.Although the gray scale level is supposed to be perceived as 127 and128, the gray scale level is perceived to be 96 or 159, and thereby apseudo contour occurs.

FIGS. 80A and 80B show a case of an 8-bit gray scale (256 gray scales).Next, FIG. 81 shows a case of a 6-bit gray scale (64 gray scales). Inthis case also, the eyes sometimes sense the gray scale level to be 16(=16), and sometimes sense the gray scale level to be 47(=1+2+4+8+16+16) in accordance with the eyes' movement. Although thegray scale level is supposed to be perceived as 31 and 32, the grayscale level is perceived to be 16 or 47, and thereby a pseudo contouroccurs.

SUMMARY OF THE INVENTION

As described above, it is difficult to realize high-definition andmultiple gray scales only by the conventional area gray scale method;and a pseudo contour occurs only by the conventional time gray scalemethod, so that deterioration of image quality cannot be sufficientlysuppressed.

In view of the foregoing problems, objects of the invention are toprovide a display device which can perform multiple gray scale displayand in which the number of subframes is small so that a pseudo contourcan be reduced; and to provide a driving method of the display device.

One feature of the invention is a driving method of a display deviceincluding a plurality of pixels each of which includes m subpixels (m isan integer of m≧2) each provided with a light emitting element. In the msubpixels, the area of the (s+1)th subpixel (1≦s≦m−1) is twice the areaof the s-th subpixel. In each lighting period of the m subpixels, oneframe is divided into n subframes (n is an integer of n≧2). In the nsubframes, a lighting period of the (p+1)th subframe (1≦p≦n−1) is 2^(m)times longer than a lighting period of the p-th subframe. At least onesubframe of the n subframes is divided into a plurality of subframeseach having a lighting period shorter than that of the subframe so thatthe n subframes are increased to t subframes (t>n). In at least onesubframe of the t subframes, lighting periods of the subframes in alighting state are sequentially added by the m subpixels, so that a grayscale of the pixel is expressed.

Note that in the driving method of the invention, a subframe having thelongest lighting period among the n subframes may be divided into aplurality of subframes each having a lighting period shorter than thatof the subframe.

Note that in the driving method of the invention, at least one subframeof the n subframes may be divided into a plurality of subframes havinglighting periods equal to each other.

Note that in the driving method of the invention, the subframes may bearranged in ascending order or descending order of the lighting periods.

Note that in the driving method of the invention, luminance may bechanged linearly with respect to the gray scale level in a low grayscale region, while luminance may be changed nonlinearly with respect tothe gray scale level in a region other than the low gray scale region.

Another feature of the invention is a display device which performs thedriving method of the invention. M subpixels each include a lightemitting element, a signal line, a scan line, a first power supply line,a second power supply line, a selection transistor, and a drivingtransistor. A first electrode of the selection transistor iselectrically connected to the signal line and a second electrode thereofis electrically connected to a gate electrode of the driving transistor.A first electrode of the driving transistor is electrically connected tothe first power supply line. A first electrode of the light emittingelement is electrically connected to a second electrode of the drivingtransistor and a second electrode thereof is electrically connected tothe second power supply line.

Note that in the display device of the invention, the signal line, thescan line, or the first power supply line may be shared in the msubpixels.

Note that in the display device of the invention, the number of thesignal lines included in a pixel may be equal to or more than two andequal to or less than m, and the selection transistor included in one ofthe m subpixels may be electrically connected to the signal linedifferent from that/those connected to the selection transistor(s)included in the other subpixel(s).

Note that in the display device of the invention, the number of the scanlines included in a pixel may be equal to or more than two, and theselection transistor included in one of the m subpixels may beelectrically connected to the scan line different from that connected tothe selection transistor included in another subpixel.

Note that in the display device of the invention, the number of thefirst power supply lines included in a pixel may be equal to or morethan 2 and equal to or less than m, and the driving transistor includedin one of the m subpixels may be electrically connected to the firstpower supply line different from that connected to the drivingtransistor included in another subpixel.

Note that division of a subframe means dividing the length of a lightingperiod included in the subframe.

Note that in the invention, lighting periods (or the frequency oflighting in a predetermined time) in subframes are sequentially added toexpress a gray scale. That is, the number of lighting subframes iscontinuously increased in accordance with increase in gray scale level.Therefore, during a lighting subframe in a case of expressing a low grayscale, light emission is also performed in a case of expressing a highergray scale. In this specification, such a gray scale method is referredto as an overlapping time gray scale method.

Note that in the invention, if at least one of the subpixels is lightedin at least one of the subframes for displaying a gray scale level of i(i denotes is an integer of i≧0), the one of the subpixels is lighted inthe one of the subframes for whenever displaying a gray scale levellarger than i.

In the invention, one pixel corresponds to one color element. Thus, in acase of a color display device having color elements of R (Red), G(Green), and B (Blue), a smallest unit of an image includes three pixelsof an R pixel, a G pixel, and a B pixel. Note that the color elementsare not limited to three colors, and color elements with more than threecolors may be used or a color other than RGB may be used. For example,RGBW may be used by adding white (W) to RGB. Alternatively, one or morecolors such as yellow, cyan, and magenta, for example, may be added toRGB. Further, a color similar to one of RGB may be added. For example,four color elements of R, G, B1, and B2 may be employed. Although B1 andB2 are both blue, they are different in wavelength. By using such colorelements, display which is closer to life can be performed and powerconsumption can be reduced. Note that brightness of each color elementmay be controlled by using a plurality of regions. In this case, onecolor element corresponds to one pixel, and each region which controlsthe brightness corresponds to a subpixel. Accordingly, in a case wheredisplay is performed by an area gray scale method, for example, onecolor element has a plurality of regions which control brightness, andall the regions are used for expressing a gray scale. In this case, eachregion which controls brightness corresponds to a subpixel. Accordingly,in such a case, one color element includes a plurality of subpixels.Further, each subpixel has a region with a different area, whichcontributes to display, in some cases. In addition, slightly differentsignals may be supplied to a plurality of regions provided in one colorelement, which control brightness, that is, a plurality of subpixelsforming one color element, so that a viewing angle may be widened.

In the invention, pixels may be provided (arranged) in matrix. Here, thedescription that pixels are provided (arranged) in matrix includes acase where pixels are provided straight or jagged linearly in thelongitudinal direction or the lateral direction. For example, in a casewhere full color display is performed with three color elements (e.g.,RGB), a case where the three color elements are arranged in stripes; anda case where dots of the three color elements are arranged in deltapattern or the Bayer arrangement are included.

Note that it is difficult to distinguish a source and a drain because ofa structure of a transistor. Further, potential level may be switcheddepending on a circuit operation. Therefore, in this specification, asource and a drain are not particularly specified and referred to as afirst electrode and a second electrode. For example, when a firstelectrode is a source, a second electrode is referred to a drain. On theother hand, when a first electrode is a drain, a second electrode isreferred to a source.

Note that in the invention, a transistor can have various modes and isnot limited to a specific type. For example, a thin film transistor(TFT) using a non-single crystalline semiconductor film typified byamorphous silicon or polycrystalline silicon can be employed.Accordingly, the following advantages can be obtained: such transistorscan be manufactured at a low manufacturing temperature, can bemanufactured at low cost, can be formed over a large substrate or alight transmitting substrate, and such transistors can transmit light.In addition, a transistor formed by using a semiconductor substrate oran SOI substrate, a junction transistor, a bipolar transistor, or thelike can be employed. Accordingly, the following advantages can beobtained: transistors with few variations can be manufactured, atransistor with a high current supply capability can be manufactured, asmall transistor can be manufactured, and a circuit with low powerconsumption can be formed. Further, a transistor including a compoundsemiconductor such as ZnO, a-InGaZnO, SiGe, or GaAs, or a thin filmtransistor obtained by thinning such a transistor can be employed.Accordingly, the following advantages can be obtained: such transistorscan be manufactured at a low manufacturing temperature or at a roomtemperature, and can be formed directly over a low heat-resistantsubstrate such as a plastic substrate or a film substrate. A transistoror the like formed by an ink-jet method or a printing method may also beemployed. Accordingly, the following advantages can be obtained:transistors can be manufactured at a room temperature or in a lowvacuum, and can be formed over a large substrate. Further, since suchtransistors can be manufactured without using a mask (reticle), a layoutof the transistors can be easily changed. A transistor including anorganic semiconductor or a carbon nanotube, or any other transistor canbe employed as well. Accordingly, transistors can be formed over asubstrate which can be bent. Note that a non-single crystallinesemiconductor film may include hydrogen or halogen. In addition, atransistor can be formed using various substrates, and a kind ofsubstrate is not particularly limited. For example, a single crystallinesubstrate, an SOI substrate, a glass substrate, a quartz substrate, aplastic substrate, a paper substrate, a cellophane substrate, a stonesubstrate, a stainless steel substrate, or the like can be used. Inaddition, after a transistor is formed using a substrate, the transistormay be transposed onto another substrate. By using such a substrate, thefollowing advantages can be obtained: a transistor with excellentproperties can be formed, a transistor with low power consumption can beformed, a device with high durability can be formed, and high heatresistance can be provided.

Note that in the invention, the description of being “connected” issynonymous with being electrically connected. Therefore, in addition toa predetermined connection relation, an element which enables anelectrical connection (e.g., another element or a switch) may beprovided in a structure disclosed in the invention.

Note that a switch shown in the invention can have various modes, suchas an electrical switch and a mechanical switch. That is, any type ofswitch can be used without being limited to a particular type as long ascurrent flow can be controlled. For example, a transistor, a diode (suchas a PN diode, a PIN diode, a Schottky diode, or a diode-connectedtransistor), a thyristor, or a logic circuit which is a combinationthereof may be used. In a case where a transistor is used as a switch,polarity (conductivity type) of the transistor is not particularlylimited because it operates as a mere switch. However, when less offcurrent is preferable, a transistor of polarity with less off current ispreferably used. As a transistor with less off current, a transistorhaving an LDD region, a transistor having a multi-gate structure, andthe like are given as an example. Further, an n-channel transistor ispreferably used when a potential of a source terminal of the transistorfunctioning as a switch is close to a low potential side power supply(VSS, GND, 0V, or the like). On the other hand, a p-channel transistoris preferably used when the potential of the source terminal is close toa high potential side power supply (VDD or the like). This is becausethe transistor can easily function as a switch since an absolute valueof a gate-source voltage can be increased. Note that a CMOS switch mayalso be applied by using both n-channel and p-channel transistors. ACMOS switch can easily function as a switch since a current can flowwhen either of the n-channel transistor or the p-channel transistor isturned on. For example, a voltage can be output as appropriate whether avoltage of an input signal to the switch is high or low. Further, avoltage amplitude value of a signal for turning on/off a switch can bedecreased; thus, power consumption can be reduced.

In the invention, the description that an object is formed on or over adifferent object does not necessarily mean that the object is in directcontact with the different object. The description includes a case wheretwo objects are not in direct contact with each other, that is, a casewhere another object is interposed therebetween. Accordingly, forexample, when it is described that a layer B is formed on (or over) alayer A, it means either case where the layer B is formed on and indirect contact with the layer A, or where another layer (e.g., a layer Cor a layer D) is formed on and in direct contact with the layer A andthe layer B is formed on and in direct contact with the layer C or D.Similarly, when it is described that an object is formed above adifferent object, it does not necessarily mean that the object is indirect contact with the different object, and another object may beinterposed therebetween. Accordingly, for example, when it is describedthat a layer B is formed above a layer A, it means either case where thelayer B is formed on and in direct contact with the layer A, or whereanother layer (e.g., a layer C or a layer D) is formed on and in directcontact with the layer A and the layer B is formed on and in directcontact with the layer C or D. Similarly, when it is described that anobject is formed under or below a different object, it means either casewhere the objects are in direct contact with each other or not incontact with each other.

Note that in the invention, a semiconductor device corresponds to adevice having a circuit which includes a semiconductor element (such asa transistor or a diode). Further, a semiconductor device may be ageneral device which can operate by using semiconductor characteristics.A display device corresponds to a device including a display element(such as a liquid crystal element or a light emitting element). Notethat a display device may be a main body of a display panel in which aplurality of pixels including a display element such as a liquid crystalelement or an EL element and a peripheral driver circuit for driving thepixels are formed over a substrate. A display device may include anelement (such as an IC, a resistor, a capacitor, an inductor, or atransistor) which is provided with a flexible printed circuit (FPC) or aprinted wiring board (PWB). Further, a display device may include anoptical sheet such as a polarizing plate or a retardation film. Inaddition, a backlight (such as a light guiding plate, a prism sheet, adiffusion sheet, a reflection sheet, or a light source (e.g., an LED, acold-cathode tube, or the like)) may be included.

Note that a display device of the invention can have various modes orincludes various display elements. For example, a display medium ofwhich contrast is changed by electromagnetic action, such as an ELelement (an organic EL element, an inorganic EL element, or an ELelement containing both organic and inorganic materials), anelectron-emissive element, a liquid crystal element, electronic ink, agrating light valve (GLV), a plasma display panel (PDP), a digitalmicromirror device (DMD), a piezoelectric ceramic display, or a carbonnanotube can be applied. Note that display devices using an EL elementinclude an EL display; display devices using an electron-emissiveelement include a field emission display (FED), an SED flat paneldisplay (SED: Surface-conduction Electron-emitter Display), and thelike; display devices using a liquid crystal element include a liquidcrystal display, a transmissive liquid crystal display, a transflectiveliquid crystal display, and a reflective liquid crystal display; anddisplay devices using electronic ink include electronic paper.

Note that a light emitting element in this specification is referred toan element among display elements, which is capable of controllingluminance depending on a current flowing through the element. Typically,the light emitting element is referred to an EL element. Other than anEL element, an electron-emissive element is also included in the lightemitting element, for example.

Note that in this specification, a case of including a light emittingelement as a display element is mainly described as an example; however,the display element is not limited to the light emitting element in thecontent of the invention. Various display elements as described abovecan be applied.

In the invention, by combination of an area gray scale method and a timegray scale method, multiple gray scale display can be performed and apseudo contour can be reduced. Accordingly, display quality can beimproved and a clear image can be obtained. Further, a duty ratio (aratio of a lighting period in one frame) can be improved as comparedwith a conventional time gray scale method, and luminance can beimproved. By improvement in the duty ratio, a voltage applied to a lightemitting element can be reduced. Therefore, power consumption can bereduced and deterioration of the light emitting element can besuppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a chart showing an example of a selection method of a subpixeland a subframe in a driving method of the invention.

FIG. 2 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 3 is a chart showing an example of a selection method of a subpixeland a subframe in a driving method of the invention.

FIG. 4 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 5 is a chart showing an example of a selection method of a subpixeland a subframe in a driving method of the invention.

FIG. 6 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 7 is a chart showing an example of a selection method of a subpixeland a subframe in a driving method of the invention.

FIG. 8 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 9 is a chart showing an example of a selection method of a subpixeland a subframe in a driving method of the invention.

FIG. 10 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 11 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 12 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 13 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 14 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 15 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 16 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 17 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 18 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 19 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 20 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 21 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 22 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 23 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 24 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 25 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 26 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 27 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 28 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention, in a casewhere gamma correction is performed.

FIGS. 29A and 29B are charts showing a relation between a gray scalelevel and luminance in a driving method of the invention, in a casewhere gamma correction is performed.

FIG. 30 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention, in a casewhere gamma correction is performed.

FIGS. 31A and 31B are charts showing a relation between a gray scalelevel and luminance in a driving method of the invention, in a casewhere gamma correction is performed.

FIG. 32 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 33 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 34 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 35 is a diagram showing a cause of reducing a pseudo contour in adriving method of the invention.

FIG. 36 is a chart showing an example of a selection method of asubpixel and a subframe in a driving method of the invention.

FIG. 37 is a diagram showing an example of a timing chart in a casewhere a period for writing a signal to a pixel and a lighting period areseparated.

FIG. 38 is a diagram showing an example of a pixel configuration in acase where a period for writing a signal to a pixel and a lightingperiod are separated.

FIG. 39 is a diagram showing an example of a pixel configuration in acase where a period for writing a signal to a pixel and a lightingperiod are separated.

FIG. 40 is a diagram showing an example of a pixel configuration in acase where a period for writing a signal to a pixel and a lightingperiod are separated.

FIG. 41 is a diagram showing an example of a timing chart in a casewhere a period for writing a signal to a pixel and a lighting period arenot separated.

FIG. 42 is a diagram showing an example of a pixel configuration in acase where a period for writing a signal to a pixel and a lightingperiod are not separated.

FIG. 43 is a diagram showing an example of a timing chart for selectingtwo rows in one gate selection period.

FIG. 44 is a diagram showing an example of a timing chart in a casewhere an operation of erasing a signal of a pixel is performed.

FIG. 45 is a diagram showing an example of a pixel configuration in acase where an operation of erasing a signal of a pixel is performed.

FIG. 46 is a diagram showing an example of a pixel configuration in acase where an operation of erasing a signal of a pixel is performed.

FIG. 47 is a diagram showing an example of a pixel configuration in acase where an operation of erasing a signal of a pixel is performed.

FIG. 48 is a diagram showing an example of a layout of a pixel portionof a display device using a driving method of the invention.

FIG. 49 is a diagram showing an example of a layout of a pixel portionof a display device using a driving method of the invention.

FIG. 50 is a diagram showing an example of a layout of a pixel portionof a display device using a driving method of the invention.

FIG. 51 is a diagram showing an example of a layout of a pixel portionof a display device using a driving method of the invention.

FIG. 52 is a diagram showing an example of a display device using adriving method of the invention.

FIG. 53 is a diagram showing an example of a display device using adriving method of the invention.

FIGS. 54A and 54B are diagrams each showing an example of a displaydevice using a driving method of the invention.

FIG. 55 is a diagram showing an example of a display device using adriving method of the invention.

FIG. 56 is a diagram showing an example of a display device using adriving method of the invention.

FIGS. 57A and 57B are diagrams showing an example of a structure of adisplay panel used for a display device of the invention.

FIG. 58 is a diagram showing an example of a structure of a lightemitting element used for a display device of the invention.

FIGS. 59A to 59C are diagrams each showing an example of a structure ofa display device of the invention.

FIG. 60 is a diagram showing an example of a structure of a displaydevice of the invention.

FIGS. 61A and 61B are diagrams each showing an example of a structure ofa display device of the invention.

FIGS. 62A and 62B are diagrams each showing an example of a structure ofa display device of the invention.

FIGS. 63A and 63B are diagrams each showing an example of a structure ofa display device of the invention.

FIGS. 64A and 64B are diagrams each showing an example of a structure ofa display device of the invention.

FIGS. 65A and 65B are diagrams each showing an example of a structure ofa display device of the invention.

FIGS. 66A and 66B are diagrams each showing an example of a structure ofa display device of the invention.

FIGS. 67A to 67C are diagrams showing a structure of a transistor usedfor a display device of the invention.

FIGS. 68A to 68D are diagrams each describing a manufacturing method ofa transistor used for a display device of the invention.

FIGS. 69A to 69C are diagrams each describing a manufacturing method ofa transistor used for a display device of the invention.

FIGS. 70A to 70D are diagrams each describing a manufacturing method ofa transistor used for a display device of the invention.

FIGS. 71A to 71D are diagrams each describing a manufacturing method ofa transistor used for a display device of the invention.

FIGS. 72A to 72D are diagrams each describing a manufacturing method ofa transistor used for a display device of the invention.

FIGS. 73A and 73B are diagrams each describing a manufacturing method ofa transistor used for a display device of the invention.

FIG. 74 is a diagram showing an example of hardware controlling adisplay device of the invention.

FIG. 75 is a diagram showing an example of an EL module using a displaydevice of the invention.

FIG. 76 is a diagram showing a structure example of a display panelusing a display device of the invention.

FIG. 77 is a diagram showing a structure example of a display panelusing a display device of the invention.

FIG. 78 is a diagram showing an example of an EL television receiverusing a display device of the invention.

FIGS. 79A to 79H are diagrams each showing an example of an electronicappliance to which a display device of the invention is applied.

FIGS. 80A and 80B are diagrams showing a cause of generation of a pseudocontour in a conventional driving method.

FIG. 81 is a diagram showing a cause of generation of a pseudo contourin a conventional driving method.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiment modes of the present invention will be describedwith reference to drawings. However, the present invention can beembodied in many different modes and it is easily understood by thoseskilled in the art that modes and details can be variously changedwithout departing from the scope and the spirit of the presentinvention. Therefore, the present invention is not construed as beinglimited to description of the embodiment modes.

Embodiment Mode 1

In this embodiment mode, an example where a driving method of theinvention is applied to a case of 6-bit display (64 gray scales) isdescribed.

A driving method according to this embodiment mode is a driving methodusing a combination of an area gray scale method in which one pixel isdivided into a plurality of subpixels and a gray scale is expressed bycontrol of the number or the area of lighting subpixels; and a time grayscale method in which one frame is divided into a plurality ofsubframes, each subframe is weighted with respect to the frequency oflight emission, a light emitting period, or the like, and then the totalweight is differentiated for each gray scale level, thereby expressing agray scale. That is, one pixel is divided into m subpixels (m is aninteger of m≧2). In the m subpixels, the area of the (s+1)th subpixel(1≦s≦m−1) is twice the area of the s-th subpixel, in other words, aratio of the area of the s-th subpixel to the area of the (s+1)thsubpixel is 1:2. Further, one frame is divided into n subframes (n is aninteger of n≧2). In the n subframes, the length of a lighting period ofthe (p+1)th subframe (1≦p≦n−1) is 2^(m) times the length of a lightingperiod of the p-th subframe. In other words, a ratio of the length ofthe lighting period of the p-th subframe to the length of the lightingperiod of the (p+1)th subframe is 1:2^(m). Further, at least onesubframe of the n subframes is divided into a plurality of subframes sothat the n subframes are increased to t subframes (t>n), and in eachsubpixel, an overlapping time gray scale method is applied to subframesof which light emission intensity is equal. That is, the number oflighting subframes is continuously increased in accordance with increasein gray scale level. A gray scale is expressed by controlling lightingof each of the m subpixels in each subframe. Note that in the invention,the product of the area of each subpixel and a lighting period of eachsubframe is light emission intensity.

First, a method of division of a subpixel and a subframe is described.In this embodiment mode, a case is described as an example, in which onepixel is divided into two subpixels (SP1 and SP2) so that an area ratioof the subpixels is 1:2; one frame is divided into three subframes (SF1,SF2, and SF3) so that a ratio of lighting period between the subframesis 1:4:16; and further, one subframe of the three subframes (SF1 to SF3)is divided into two subframes. Note that in this example, m=2 and n=3.

Here, the subpixels have the following areas: SP1=1 and SP2=2, and thesubframes have the following lighting periods: SF1=1, SF2=4, and SF3=16.

In this embodiment mode, one subframe of the subframes (SF1 to SF3)obtained by being divided into three subframes so that a ratio of thelighting periods is 1:4:16, is further divided into two subframes. Forexample, when SF3 is a subframe to be divided into two subframes, SF3having the lighting period of 16 is divided into two subframes SF31 andSF32 each having a lighting period of 8.

Thus, one frame is divided into four subframes, and the lighting periodof each subframe is SF1=1, SF2=4, SF31=8, and SF32=8.

FIG. 1 shows an example of a selection method of a subpixel and asubframe for expressing each gray scale in this case. In FIG. 1, in eachsubframe, a subpixel marked by a circle indicates that it is lit and asubpixel marked by a cross indicates that it is not lit.

In the invention, it is considered that the product of the area of eachsubpixel and a lighting period of each subframe is light emissionintensity. In FIG. 1, for example, in SF1 having the lighting period of1, when only the subpixel 1 (SP1) with the area of 1 is lit, lightemission intensity is 1×1=1; and when only the subpixel 2 (SP2) with thearea of 2 is lit, light emission intensity is 2×1=2. Similarly in SF2having the lighting period of 4, when only SP1 is lit, light emissionintensity is 4; and when only SP2 is lit, light emission intensity is 8.Similarly in SF31 and SF32 having the lighting period of 8, when onlySP1 is lit, light emission intensity is 8; and when only SP2 is lit,light emission intensity is 16. As described above, different lightemission intensity can be made depending on a combination of the area ofa subpixel and a lighting period of a subframe, and a gray scale isexpressed by using this light emission intensity.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 1, since light emission intensity of SP1 is8 in SF31 and SF32, the overlapping time gray scale method is applied toSF31 and SF32. That is, SP1 is always lit in SF31 when a gray scale at agray scale level of 8 or more is expressed, and always lit in SF32 whena gray scale at a gray scale level of 16 or more is expressed.Similarly, since light emission intensity of SP2 is 16 in SF31 and SF32,the overlapping time gray scale method is applied to SF31 and SF32. Thatis, SP2 is always lit in SF31 when a gray scale at a gray scale level of32 or more is expressed, and always lit in SF32 when a gray scale of 48or more is expressed.

Next, a selection method of a subpixel and a subframe for expressingeach gray scale is described.

For example, in the selection method of the subpixel and the subframeshown in FIG. 1, when a gray scale of 1 is expressed, SP1 is lit in SF1.When a gray scale of 2 is expressed, SP2 is lit in SF1. When a grayscale of 3 is expressed, SP1 and SP2 are lit in SF1. When a gray scaleof 6 is expressed, SP2 is lit in SF1 and SP1 is lit in SF2. When a grayscale of 32 is expressed, SP1 and SP2 are lit in SF31 and SP1 is lit inSF32. Similarly, when any other gray scale is expressed, each subpixelis selected in each subframe.

As described above, a 6-bit gray scale (64 gray scales) can be expressedby selection of a subpixel lit in each subframe.

By using a driving method of the invention, a pseudo contour can bereduced as compared with a conventional driving method. For example, apixel A displays an image at a gray scale level of 31 and a pixel Bdisplays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 1.

FIG. 2 shows a lighting or non-lighting state of each subpixel in eachsubframe in this case.

Here, how to interpret FIG. 2 is described. FIG. 2 shows a lighting ornon-lighting state of a pixel in one frame. The horizontal direction ofFIG. 2 indicates time, and the vertical direction thereof indicates aposition of the pixel. The length of the horizontal direction of asquare in FIG. 2 indicates an area ratio of each subpixel, and thelength of the vertical direction thereof indicates a ratio of the lengthof a lighting period in each subframe. The area of each square in FIG. 2indicates light emission intensity.

For example, when a line of sight is moved, a gray scale level issometimes perceived as 29 (=1+4+8+8+8), and the gray scale level issometimes perceived as 32 (=16+8+8) depending on a movement of the lineof sight. Although the gray scale level is supposed to be perceived as31 and 32, the gray scale level is perceived to be 29 or 32, and therebya pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

Note that the length of a lighting period is changed as appropriate inaccordance with the total number of gray scales (the number of bits),the total number of subframes, or the like. Therefore, if the totalnumber of gray scales (the number of bits) or the total number ofsubframes is changed, the length of a period for actually lighting(e.g., the size of μs) may be changed even when the length of thelighting period is the same.

Note that a lighting period is used when a pixel is lit continuously,and the frequency of lighting is used when a pixel is flashed on and offrepeatedly in a certain period. A typical display using the frequency oflighting is a plasma display, and a typical display using a lightingperiod is an organic EL display.

Note that although SF3 is divided into two subframes in the exampleshown in FIG. 1, SF3 may be divided into three or more subframes. FIG. 3shows a selection method of a subpixel and a subframe in a case whereSF3 in FIG. 1 is divided into four subframes, for example.

In an example shown in FIG. 3, SF3 having a lighting period of 16 amongthe subframes (SF1 to SF3) obtained by being divided into threesubframes so that a ratio of the lighting periods is 1:4:16, is dividedinto four subframes SF31, SF32, SF33, and SF34 each having a lightingperiod of 4.

Thus, one frame is divided into six subframes, and the lighting periodof each subframe is SF1=1, SF2=4, SF31=4, SF32=4, SF33=4, and SF34=4.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 3, since light emission intensity of SP1 is4 in SF2, and SF31 to SF34, the overlapping time gray scale method isapplied to SF2, and SF31 to SF33 among these subframes. That is, SP1 isalways lit in SF2 when a gray scale at a gray scale level of 4 or moreis expressed, always lit in SF31 when a gray scale at a gray scale levelof 8 or more is expressed, always lit in SF32 when a gray scale at agray scale level of 12 or more is expressed, and always lit in SF33 whena gray scale at a gray scale level of 16 or more is expressed.Similarly, since light emission intensity of SP2 is 8 in SF2, and SF31to SF34, the overlapping time gray scale method is applied to SF2, andSF31 to SF34.

Note that as shown in FIG. 3, when the overlapping time gray scalemethod is applied to subframes of which light emission intensity isequal in each subpixel, the overlapping time gray scale method isapplied to at least one subframe among the corresponding subframes.Therefore, the overlapping time gray scale method may be applied to aplurality or all of the corresponding subframes.

When a driving method shown in FIG. 3 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 3. FIG. 4 shows alighting or non-lighting state of each subpixel in each subframe in thiscase. For example, when a line of sight is moved, a gray scale level issometimes perceived as 21 (=1+4+8+4+4), and the gray scale level issometimes perceived as 28 (=8+8+4+4+4) depending on a movement of theline of sight. Although the gray scale level is supposed to be perceivedas 31 and 32, the gray scale level is perceived to be 21 or 28, andthereby a pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

As the example shown in FIG. 3, when the number of division of SF3 isincreased, the number of subframes having a longest lighting period isincreased and the number of subframes without requiring an erasingoperation is increased; thus, power consumption for an erasing operationcan be reduced. Further, a duty ratio can be improved, and luminance canbe improved. By improvement in duty ratio, a voltage applied to a lightemitting element can be reduced. Therefore, power consumption can bereduced and deterioration of the light emitting element can besuppressed.

Note that although SF3 is divided into a plurality of subframes eachhaving the same lighting period in FIGS. 1 and 3, the invention is notlimited thereto; SF3 may be divided into a plurality of subframes eachhaving a different lighting period. FIG. 5 shows a selection method of asubpixel and a subframe in a case where SF3 in FIG. 1 is divided intotwo subframes each having a different lighting period.

In FIG. 5, SF3 having the lighting period of 16 among the subframes (SF1to SF3) obtained by being divided into three subframes so that a ratioof the lighting periods is 1:4:16, is divided into a subframe SF31having a lighting period of 4 and a subframe SF32 having a lightingperiod of 12.

Thus, one frame is divided into four subframes, and the lighting periodof each subframe is SF1=1, SF2=4, SF31=4, and SF32=12.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 5, since light emission intensity of SP1 is4 in SF2 and SF31, the overlapping time gray scale method is applied toSF2 among these subframes. That is, SP1 is always lit in SF2 when a grayscale at a gray scale level of 4 or more is expressed. Similarly, sincelight emission intensity of SP2 is 8 in SF2 and SF31, the overlappingtime gray scale method is applied to SF2 among these subframes.

When a driving method shown in FIG. 5 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 5. FIG. 6 shows alighting or non-lighting state of each subpixel in each subframe in thiscase. For example, when a line of sight is moved, a gray scale level issometimes perceived as 25 (=1+4+8+12), and the gray scale level issometimes perceived as 28 (=8+8+12) depending on a movement of the lineof sight. Although the gray scale level is supposed to be perceived as31 and 32, the gray scale level is perceived to be 25 or 28, and therebya pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

FIGS. 7 and 9 each show a selection method of a subpixel and a subframein a case where SF3 in FIG. 1 is divided into three subframes eachhaving a different lighting period.

In FIG. 7, SF3 having the lighting period of 16 among the subframes (SF1to SF3) obtained by being divided into three subframes so that a ratioof the lighting periods is 1:4:16, is divided into subframes SF31 andSF32 each having a lighting period of 4 and a subframe SF33 having alighting period of 8.

Thus, one frame is divided into five subframes, and the lighting periodof each subframe is SF1=1, SF2=4, SF31=4, SF32=4, and SF33=8.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In FIG. 7, since light emission intensity of SP1 is 4 in SF2, SF31, andSF32, the overlapping time gray scale method is applied to SF2 and SF31among these subframes. That is, SP1 is always lit in SF2 when a grayscale at a gray scale level of 4 or more is expressed, and always lit inSF31 when a gray scale at a gray scale level of 8 or more is expressed.Similarly, since light emission intensity of SP2 is 8 in SF2, SF31, andSF32, the overlapping time gray scale method is applied to SF2, SF31,and SF32.

When a driving method shown in FIG. 7 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 7. FIG. 8 shows alighting or non-lighting state of each subpixel in each subframe in thiscase. For example, when a line of sight is moved, a gray scale level issometimes perceived as 20 (=8+8+4), and the gray scale level issometimes perceived as 29 (=1+4+8+8+8) depending on a movement of theline of sight. Although the gray scale level is supposed to be perceivedas 31 and 32, the gray scale level is perceived to be 20 or 29, andthereby a pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

In FIG. 9, SF3 having the lighting period of 16 among the subframes (SF1to SF3) obtained by being divided into three subframes so that a ratioof the lighting periods is 1:4:16, is divided into a subframe SF31having a lighting period of 4 and subframes SF32 and SF33 each having alighting period of 6.

Thus, one frame is divided into five subframes, and the lighting periodof each subframe is SF1=1, SF2=4, SF31=4, SF32=6, and SF33=6.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the case of the example shown in FIG. 9, since light emissionintensity of SP1 is 4 in SF2 and SF31, the overlapping time gray scalemethod is applied to SF2 among these subfranies. Further, since lightemission intensity of SP1 is 6 in SF32 and SF33, the overlapping timegray scale method is applied to SF32 and SF33. That is, SP1 is alwayslit in SF2 when a gray scale at a gray scale level of 4 or more isexpressed, always lit in SF32 when a gray scale at a gray scale level of12 or more is expressed, and always lit in SF33 when a gray scale at agray scale level of 18 or more is expressed. Similarly, since lightemission intensity of SP2 is 8 in SF2 and SF31, the overlapping timegray scale method is applied to SF2 among these subframes. Further,since light emission intensity of SP2 is 12 in SF32 and SF33, theoverlapping time gray scale method is applied to SF32 and SF33.

When a driving method shown in FIG. 9 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 9. FIG. 10 shows alighting or non-lighting state of each subpixel in each subframe in thiscase. For example, when a line of sight is moved, a gray scale level issometimes perceived as 25 (=1+4+8+6+6), and the gray scale level issometimes perceived as 28 (=8+8+6+6) depending on a movement of the lineof sight. Although the gray scale level is supposed to be perceived as31 and 32, the gray scale level is perceived to be 25 or 28, and therebya pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

Note that although one subframe (SF3) of SF1 to SF3 is further dividedinto a plurality of subframes in FIG. 9, the number of subframes to bedivided into a plurality of subframes is not limited thereto. Aplurality of subframes of SF1 to SF3 may each be divided into aplurality of subpixels.

FIGS. 11 and 13 each show a case where two subframes of the subframes(SF1 to SF3) in FIG. 1 obtained by being divided into three subframes sothat a ratio of the lighting periods is 1:4:16, are further divided intoa plurality of subframes. In FIGS. 11 and 13, subframes to be dividedinto a plurality of subframes are SF2 and SF3.

FIG. 11 shows a case where SF2 and SF3 each are divided into twosubframes. For example, SF2 having a lighting period of 4 is dividedinto two subframes SF21 and SF22 each having a lighting period of 2. SF3having a lighting period of 16 is divided into two subframes SF31 andSF32 each having a lighting period of 8.

Thus, one frame is divided into five subframes, and the lighting periodof each subframe is SF1=1, SF21=2, SF22=2, SF31=8, and SF32=8.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 11, since light emission intensity of SP1is 2 in SF21 and SF22, the overlapping time gray scale method is appliedto SF21 and SF22. Further, since light emission intensity of SP1 is 8 inSF31 and SF32, the overlapping time gray scale method is applied to SF32among these subframes. That is, SP1 is always lit in SF21 when a grayscale at a gray scale level of 2 or more is expressed, always lit inSF22 when a gray scale at a gray scale level of 4 or more is expressed,and always lit in SF31 when a gray scale at a gray scale level of 16 ormore is expressed. Similarly, since light emission intensity of SP2 is 4in SF21 and SF22, the overlapping time gray scale method is applied toSF21 among these subframes. Further, since light emission intensity ofSP2 is 16 in SF31 and SF32, the overlapping time gray scale method isapplied to SF31 and SF32.

When a driving method shown in FIG. 11 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of. 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 11. FIG. 12 showsa lighting or non-lighting, state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 19 (=1+2+4+4+8), and the gray scalelevel is sometimes perceived as 28 (=4+16+8) depending on a movement ofthe line of sight. Although the gray scale level is supposed to beperceived as 31 and 32, the gray scale level is perceived to be 19 or28, and thereby a pseudo contour occurs. However, a gray scale gap isreduced as compared with the conventional driving method; thus, a pseudocontour is reduced.

FIG. 13 shows a case where SF2 is divided into two subframes and SF3 isdivided into four subframes. For example, SF2 having a lighting periodof 4 is divided into two subframes SF21 and SF22 each having a lightingperiod of 2. SF3 having a lighting period of 16 is divided into foursubframes SF31, SF32, SF33, and SF34 each having a lighting period of 4.

Thus, one frame is divided into seven subframes, and the lighting periodof each subframe is SF1=1, SF21=2, SF22=2, SF31=4, SF32=4, SF33=4, andSF34=4.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 13, since light emission intensity of SP1is 2 in SF21 and SF22, the overlapping time gray scale method is appliedto SF21 and SF22. Further, since light emission intensity of SP1 is 4 inSF31 to SF34, the overlapping time gray scale method is applied to SF31to SF34. That is, SP1 is always lit in SF21 when a gray scale at a grayscale level of 2 or more is expressed, always lit in SF22 when a grayscale at a gray scale level of 4 or more is expressed, always lit inSF31 when a gray scale at a gray scale level of 8 or more is expressed,always lit in SF32 when a gray scale at a gray scale level of 12 or moreis expressed, always lit in SF33 when a gray scale at a gray scale levelof 16 or more is expressed, and always lit in SF34 when a gray scale ata gray scale level of 20 or more is expressed. Similarly, since lightemission intensity of SP2 is 4 in SF21 and SF22, the overlapping timegray scale method is applied to SF21 among these subframes. Further,since light emission intensity of SP2 is 8 in SF31 to SF34, theoverlapping time gray scale method is applied to SF31 to SF34.

When a driving method shown in FIG. 13 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 13. FIG. 14 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 19 (=1+2+4+4+4+4), and the gray scalelevel is sometimes perceived as 24 (=4+8+4+4+4) depending on a movementof the line of sight. Although the gray scale level is supposed to beperceived as 31 and 32, the gray scale level is perceived to be 19 or24, and thereby a pseudo contour occurs. However, a gray scale gap isreduced as compared with the conventional driving method; thus, a pseudocontour is reduced.

Note that although in the example described above, SF3 is alwaysselected as a subframe to be divided into a plurality of subframes, itis not limited thereto. A subframe to be divided into a plurality ofsubframes may be selected from SF1 and SF2.

Note that in this embodiment mode, a subframe having the longestlighting period among the n subframes is preferably selected as asubframe to be divided into a plurality of subframes. This is because bydividing a subframe having the longest lighting period, a pseudo contourcan be further reduced; and the number of subframes having the longestlighting period is increased after division and the number of subframeswithout requiring an erasing operation is increased, so that powerconsumption for an erasing operation can be reduced. Further, a dutyratio can be improved, and luminance can be improved. By improvement induty ratio, a voltage applied to the light emitting element can bereduced. Therefore, power consumption can be reduced and deteriorationof the light emitting element can be suppressed.

Note that by dividing a subframe into a plurality of subframes, thenumber of selection methods of a subpixel and a subframe for expressingthe same gray scale is increased. Accordingly, a selection method of asubpixel and a subframe is not limited to the examples described above.For example, FIG. 15 shows a case where the selection method of thesubpixel and the subframe for expressing gray scales of 31 and 32 inFIG. 1 is changed.

Differences between the selection methods of the subpixel and thesubframe in FIGS. 1 and 15 are described. First, when expressing a grayscale of 31, SP1 is lit in SF31 and SF32 in FIG. 1, while SP1 is not litin SF31 and SF32 and SP2 is lit in SF31 in FIG. 15. Second, whenexpressing a gray scale of 32, SP1 is lit in SF31 in FIG. 1, while SP1is not lit in SF31 and SP2 is lit in SF2 in FIG. 15.

The overlapping time gray scale method is applied to SF31 and SF32 inboth SP1 and SP2 in FIG. 1, while the overlapping time gray scale methodis applied to SF31 and SF32 in SP2 in FIG. 15.

When a driving method shown in FIG. 15 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 15. FIG. 16 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 37 (=1+4+8+16+8), and the gray scalelevel is sometimes perceived as 40 (=8+16+16) depending on a movement ofthe line of sight. Although the gray scale level is supposed to beperceived as 31 and 32, the gray scale level is perceived to be 37 or40, and thereby a pseudo contour occurs. However, a gray scale gap isreduced as compared with the conventional driving method; thus, a pseudocontour is reduced.

Note that a gray scale for which a selection method of a subpixel and asubframe is changed is not limited to the gray scales of 31 and 32. Amethod of a subpixel and a subframe may be changed with respect to othergray scales. Note that by selectively changing a selection method of asubpixel and a subframe with respect to a gray scale at which a pseudocontour is particularly likely to occur, such as the gray scales of 31and 32, an effect of reducing a pseudo contour can be increased.

Note that in this embodiment mode, although subframes are arranged inascending order of the lighting periods, order of arrangement ofsubframes is not limited thereto. For example, FIG. 17 shows a casewhere order of arrangement of the subframes in FIG. 1 is changed.

In FIG. 17, SF2 having a lighting period of 4 and SF32 having a lightingperiod of 8 in FIG. 1 are replaced with each other.

When a driving method shown in FIG. 17 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 17. FIG. 18 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 28 (=8+8+8+4), and the gray scale levelis sometimes perceived as 33 (=1+8+8+16) depending on a movement of theline of sight. Although the gray scale level is supposed to be perceivedas 31 and 32, the gray scale level is perceived to be 28 or 33, andthereby a pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

By changing order of arrangement of the subframes as described above,the eyes are tricked, and a gray scale gap which occurs when a line ofsight is moved can be reduced as compared with the conventional drivingmethod. Accordingly, a pseudo contour can be reduced as compared withthe conventional driving method.

Note that although SF2 and SF32 are replaced with each other in FIG. 17,subframes to be replaced are not limited thereto. A plurality ofsubframes may be optionally selected to be replaced. Note that asubframe having the longest lighting period is preferably selected as asubframe to be replaced. This is because by changing the position of thesubframe having the longest lighting period, the eyes are tricked; thus,a gray scale gap which occurs when a line of sight is moved can bereduced as compared with the conventional driving method, and a pseudocontour can be reduced as compared with the conventional driving method.

Note that subframes are preferably arranged in ascending order ordescending order of the lighting periods. This is because a gray scalegap can be reduced as compared with the conventional driving method, anda pseudo contour can be reduced as compared with the conventionaldriving method.

Note that in this embodiment mode, an area ratio of subpixels is 1:2;however, the invention is not limited thereto. For example, the arearatio may be 1:4 or 1:8.

For example, if an area ratio of subpixels is 1:1, light emissionintensity is the same when either subpixel emits light in the samesubframe. Therefore, when the same gray scale is expressed, the subpixelto emit light may be switched. Accordingly, light emission only by aspecific subpixel intensively can be prevented, and burn-in can beprevented.

Note that in the m subpixels (m is an integer of m≧2), the area of the(s+1)th subpixel (1≦s≦m−1) is twice the area of the s-th subpixel. Inother words, a ratio of the area of the s-th subpixel to the area of the(s+1)th subpixel is 1:2. Further, in the n subframes (n is an integer ofn≧2), the lighting period of the (p+1)th subframe (1≦p≦n−1) is 2^(m)times longer than the lighting period of the p-th subframe. In otherwords, a ratio of the length of the lighting period of the p-th subframeto the length of the lighting period of the (p+1)th subframe is 1:2^(m).Thus, a larger number of gray scales can be expressed with a smallernumber of subpixels and a smaller number of subframes. Further, since agray scale which can be expressed by this method has a constant rate ofchange, it is possible to perform more smooth gray scale display and toimprove image quality.

Note that in this embodiment mode, the number of subpixels is two;however, the invention is not limited thereto.

A case is described as an example, in which one pixel is divided intothree subpixels (SP1, SP2, and SP3) so that an area ratio of thesubpixels is 1:2:4; one frame is divided into two subframes (SF1 andSF2) so that a ratio of lighting period between the subframes is 1:8;and further, one subframe of the two subframe (SF1 and SF2) is dividedinto two subframes. FIG. 19 shows a selection method of a subpixel and asubframe in this case. Note that in this example, m=3 and n=2.

Here, the subpixels have the following areas: SP1=1, SP2=2, and SP3=4,and the subframes have the following lighting periods: SF1=1 and SF2=8.

In FIG. 19, one subframe of the subframes (SF1 and SF2) obtained bybeing divided into two subframes so that a ratio of the lighting periodsis 1:8, is further divided into two subframes. For example, when SF2 isa subframe to be divided into two subframes, SF2 having a lightingperiod of 8 is divided into two subframes SF21 and SF22 each having alighting period of 4.

Thus, one frame is divided into three subframes, and the lighting periodof each subframe is SF1=1, SF21=4, and SF22=4.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 19, since light emission intensity of SP1is 4 in SF21 and SF22, the overlapping time gray scale method is appliedto SF21 and SF22. That is, SP1 is always lit in SF21 when a gray scaleat a gray scale level of 4 or more is expressed, and always lit in SF22when a gray scale at a gray scale level of 8 or more is expressed.Similarly, since light emission intensity of SP2 is 8 in SF21 and SF22,the overlapping time gray scale method is applied to SF21 among thesesubframes. Similarly, since light emission intensity of SP3 is 16 inSF21 and SF22, the overlapping time gray scale method is applied to SF21and SF22.

When a driving method shown in FIG. 19 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 19. FIG. 20 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 19 (=1+2+8+4+4), and the gray scalelevel is sometimes perceived as 36 (=16+8+4+8) depending on a movementof the line of sight. Although the gray scale level is supposed to beperceived as 31 and 32, the gray scale level is perceived to be 19 or36, and thereby a pseudo contour occurs. However, a gray scale gap isreduced as compared with the conventional driving method; thus, a pseudocontour is reduced.

Note that although SF2 is divided into two substrates in FIG. 19, SF2may be divided into three or more subframes. FIG. 21 shows a selectionmethod of a subpixel and a subframe in a case where SF2 in FIG. 19 isdivided into four subframes.

In FIG. 21, SF2 having a lighting period of 8 among the subframes (SF1and SF2) obtained by being divided into two subframes so that a ratio ofthe lighting periods is 1:8, is further divided into four subframesSF21, SF22, SF23, and SF24 each having a lighting period of 2.

Thus, one frame is divided into five subframes, and the lighting periodof each subframe is SF1=1, SF21=2, SF22=2, SF23=2, and SF24=2.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIG. 21, since light emission intensity of SP1is 2 in SF21 to SF24, the overlapping time gray scale method is appliedto SF21 to SF24. That is, SP1 is always lit in SF21 when a gray scale ata gray scale level of 2 or more is expressed, always lit in SF22 when agray scale at a gray scale level of 4 or more is expressed, always litin SF23 when a gray scale at a gray scale level of 6 or more isexpressed, and always lit in SF24 when a gray scale at a gray scalelevel of 8 or more is expressed. Similarly, since light emissionintensity of SP2 is 4 in SF21 to SF24, the overlapping time gray scalemethod is applied to SF21 to SF24. Similarly, since light emissionintensity of SP3 is 8 in SF21 to SF24, the overlapping time gray scalemethod is applied to SF21 to SF24.

When a driving method shown in FIG. 21 is used, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 31 and the pixelB displays an image at a gray scale level of 32 by using the selectionmethod of the subpixel and the subframe shown in FIG. 21. FIG. 22 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 17 (=1+2+4+2+4+4), and the gray scalelevel is sometimes perceived as 24 (=8+4+4+2+4+2) depending on amovement of the line of sight. Although the gray scale level is supposedto be perceived as 31 and 32, the gray scale level is perceived to be 17or 24, and thereby a pseudo contour occurs. However, a gray scale gap isreduced as compared with the conventional driving method; thus, a pseudocontour is reduced.

As the example shown in FIG. 21, when the number of division of SF2 isincreased, the number of subframes having the longest lighting period isincreased and the number of subframes without requiring an erasingoperation is increased; therefore, power consumption for an erasingoperation can be reduced. Further, a duty ratio can be improved, andluminance can be improved. By improvement in duty ratio, a voltageapplied to the light emitting element can be reduced. Therefore, powerconsumption can be reduced and deterioration of the light emittingelement can be suppressed.

Note that a selection method of a subpixel and a subframe may be changedin a certain gray scale in accordance with time or place. In otherwords, a selection method of a subpixel and a subframe may be changeddepending on time or a pixel. Alternatively, a selection method of asubpixel and a subframe may be changed depending on time and a pixel.

For example, when a certain gray scale is expressed, a selection methodof a subpixel in each subframe may be different in the odd-numberedframe and the even-numbered frame. For example, a gray scale may beexpressed by the selection method of the subpixel and the subframe shownin FIG. 1 in the odd-numbered frame, while a gray scale may be expressedby the selection method of the subpixel and the subframe shown in FIG.15 in the even-numbered frame.

By changing a selection method of a subpixel and a subframe between theodd-numbered frame and the even-numbered frame when expressing a grayscale at which a pseudo contour is particularly likely to occur asdescribed above, a pseudo contour can be reduced.

Further, when a certain gray scale is expressed, a selection method of asubpixel and a subframe may be changed between a case of displayingpixels in the odd-numbered row and a case of displaying pixels in theeven-numbered row. Further, when a certain gray scale is expressed, aselection method of a subpixel and a subframe may be changed between acase of displaying pixels in the odd-numbered column and a case ofdisplaying in the even-numbered column.

Further, when a certain gray scale is expressed, the number of subframesor a ratio of lighting periods may be changed between the odd-numberedframe and the even-numbered frame. For example, a gray scale may beexpressed by the selection method of the subpixel shown in FIG. 1 in theodd-numbered frame, while a gray scale may be expressed by the selectionmethod of the subpixel shown in FIG. 3 in the even-numbered frame.

Further, when a certain gray scale is expressed, the number of subframesor a ratio of lighting periods may be changed between a case ofdisplaying pixels in the odd-numbered row and a case of displayingpixels in the even-numbered row. Further, when a certain gray scale isexpressed, the number of subframes or a ratio of lighting periods may bechanged between a case of displaying pixels in the odd-numbered columnand a case of displaying pixels in the even-numbered column.

Further, when a certain gray scale is expressed, order of arrangement ofsubframes may be changed between the odd-numbered frame and theeven-numbered frame. For example, a gray scale may be expressed by theselection method of the subpixel and the subframe shown in FIG. 1 in theodd-numbered frame, while a gray scale may be expressed by the selectionmethod of the subpixel and the subframe shown in FIG. 17 in theeven-numbered frame.

Further, when a certain gray scale is expressed, order of arrangement ofsubframes may be changed between a case of displaying pixels in theodd-numbered row and a case of displaying pixels in the even-numberedrow. Further, when a certain gray scale is expressed, order ofarrangement of subframes may be changed between a case of displayingpixels in the odd-numbered column and a case of displaying pixels in theeven-numbered column.

As described above, by changing a selection method of a subpixel and asubframe, the number of subframes, a ratio of lighting periods, or orderof arrangement of subframes in a certain gray scale in accordance withtime or place, the eyes are tricked and a gray scale gap can be reduced,and thereby a pseudo contour can be reduced as compared with theconventional driving method.

Note that although this embodiment mode shows a case of a 6-bit grayscale (64 gray scales), the number of gray scale levels to be displayedis not limited thereto. For example, an 8-bit gray scale (256 grayscales) can be expressed by using a driving method of the invention.FIGS. 23 to 26 show this case. FIG. 23 shows a selection method of asubpixel at gray scales of 0 to 63. FIG. 24 shows a selection method ofa subpixel at gray scales of 64 to 127. FIG. 25 shows a selection methodof a subpixel at gray scales of 128 to 191. FIG. 26 shows a selectionmethod of a subpixel at gray scales of 192 to 255.

In FIGS. 23 to 26, one pixel is divided into two subpixels (SP1 and SP2)so that an area ratio of the subpixels is 1:2; one frame is divided intofour subframes (SF1 to SF4) so that a ratio of lighting period betweenthe subframes is 1:4:16:64; and further, one subframe of the foursubframes (SF1 to SF4) is divided into two subframes. Note that in thisexample, m=2 and n=4.

Here, the subpixels have the following areas: SP1=1 and SP2=2, and thesubframes have the following lighting periods: SF1=1, SF2=4, SF3=16, andSF4=64.

In FIGS. 23 to 26, SF4 is a subframe to be divided into two subframes,and SF4 having a lighting period of 64 is divided into two subframesSF41 and SF42 each having a lighting period of 32.

Thus, one frame is divided into five subframes, and the lighting periodof each subframe is SF1=1, SF2=4, SF3=16, SF41=32, and SF42=32.

Note that in each subpixel, the overlapping time gray scale method isapplied to subframes of which light emission intensity is equal. Thatis, the number of lighting subframes is continuously increased inaccordance with increase in gray scale level, and a lighting subframe ina low gray scale level is kept to be used for lighting in a high grayscale level.

In the example shown in FIGS. 23 to 26, since light emission intensityof SP1 is 32 in SF41 and SF42, the overlapping time gray scale method isapplied to SF41 and SF42. That is, SP1 is always lit in SF41 when a grayscale at a gray scale level of 32 or more is expressed, and always litin SF42 when a gray scale at a gray scale level of 64 or more isexpressed. Similarly, since light emission intensity of SP2 is 64 inSF41 and SF42, the overlapping time gray scale method is applied to SF41and SF42.

As described above, each subpixel to be lit in each subframe isselected, so that an 8-bit gray scale (256 gray scales) can beexpressed.

When a driving method shown in FIGS. 23 to 26 is used, a pseudo contourcan be reduced as compared with the conventional driving method. Forexample, the pixel A displays an image at a gray scale level of 127 andthe pixel B displays an image at a gray scale level of 128 by using theselection methods of the subpixel and the subframe shown in FIGS. 23 to26. FIG. 27 shows a lighting or non-lighting state of each subpixel ineach subframe in this case. For example, when a line of sight is moved,a gray scale level is sometimes perceived as 109 (=1+4+8+32+32+32), andthe gray scale level is sometimes perceived as 128 (=64+32+32) dependingon a movement of the line of sight. Although the gray scale level issupposed to be perceived as 127 and 128, the gray scale level isperceived to be 109 or 128, and thereby a pseudo contour occurs.However, a gray scale gap is reduced as compared with the conventionaldriving method; thus, a pseudo contour is reduced.

As described above, by using the driving method of this embodiment mode,a pseudo contour can be reduced as compared with the conventionaldriving method. Further, a duty ratio can be improved, and luminance canbe improved. By improvement in duty ratio, power consumption can bereduced and deterioration of the light emitting element can besuppressed.

Note that the content described above, such as gray scale levels to bedisplayed, the ratio and division of lighting period of a subframe,order of arrangement of subframes, the area ratio and the number ofsubpixels, and change of a selection method of a subpixel and a subframein accordance with a gray scale level can be used in combination.

Embodiment Mode 2

In Embodiment Mode 1, a case where a lighting period increases in linearproportion to the increase of a gray scale level is described. In thisembodiment mode, a case where gamma correction is performed isdescribed.

Gamma correction is referred to a method by which a lighting periodincreases nonlinearly as a gray scale level increases. Human eyes cannotsense that luminance increases in proportion even when luminanceincreases in linear proportion. As luminance increases, difference ofbrightness is less visible to human eyes. Therefore, in order to sensethe difference of brightness by human eyes, it is necessary to increasea lighting period as a gray scale level increases, that is, gammacorrection is necessary to be performed. When a gray scale level isrepresented by x and luminance is represented by y, a relation betweenthe luminance and the gray scale level is expressed by Formula 1.

[Formula 1]

y=Ax^(γ)  (1)

Note that in Formula 1, A is a constant for normalizing the luminance yto be within a range of 0≦y≦1, and γ which is an exponent of the grayscale level x is a parameter indicating the degree of gamma correction.

As the simplest method, there is a method where display can be performedwith a larger number of bits (higher gray scale levels) than the numberof bits (gray scale levels) which are actually displayed. For example,in a case where display is performed with a 6-bit gray scale (64 grayscales), an 8-bit gray scale (256 gray scales) is actually set to bedisplayed. When an image is actually displayed, display is performedwith a 6-bit gray scale (64 gray scales) so that the luminance at thegray scale levels has a nonlinear shape. Thus, gamma correction can beperformed.

As an example, FIG. 28 shows a selection method of a subpixel and asubframe in a case where a 6-bit gray scale (64 gray scales) is set tobe displayed so that gamma correction is performed when a 5-bit grayscale (32 gray scales) is displayed.

In this embodiment mode, a case is described as an example, in which onepixel is divided into two subpixels (SP1 and SP2) so that an area ratioof the subpixels is 1:2; one frame is divided into three subframes (SF1,SF2, and SF3) so that a ratio of lighting period between the subframesis 1:4:16; and further, one subframe of the three subframes (SF1 to SF3)is divided into two subframes. As a specific example, a case of usingthe selection method of the subpixel and the subframe shown in FIG. 1 isdescribed.

FIG. 28 shows a selection method of a subpixel and a subframe in a casewhere a 5-bit gray scale (32 gray scales) is expressed by performinggamma correction so that γ=2.2 is satisfied at all the gray scalelevels. Note that γ=2.2 is a value which can best correctcharacteristics of human visual perception, with which human eyes canperceive the most appropriate difference in brightness even when theluminance becomes higher. In FIG. 28, up to a gray scale of 3 in the5-bit gray scale with gamma correction, display is actually performed bythe selection method of the subpixel and the subframe for displaying agray scale of 0 in a 6-bit gray scale. Similarly, in a case of a grayscale of 4 in the 5-bit gray scale with gamma correction, display isactually performed by displaying a gray scale of 1 in the 6-bit grayscale; and in a case of a gray scale of 6 in the 5 bit-gray scale withgamma correction, display is actually performed by displaying a grayscale of 2 in the 6 bit-gray scale. FIGS. 29A and 29B are graphs showingthe relation between the gray scale x and the luminance y. FIG. 29A is agraph showing the relation between the gray scale x and the luminance yat all the gray scales, while FIG. 29B is a graph showing the relationbetween the gray scale x and the luminance y at a low gray scale region.In this manner, a subpixel and a subframe are selected in accordancewith a correspondence table between the 5-bit gray scale with gammacorrection and the 6-bit gray scale, and display is performed.Accordingly, gamma correction which can satisfy γ=2.2 can be realized.

However, as is apparent from FIG. 29B, display can be performed at thesame luminance at the gray scale levels of 0 to 3, 4 and 5, and 6 and 7in the case of FIG. 28. This is because difference in luminance cannotbe expressed since the gray scale levels are not enough in the case of6-bit display. As measures against this, the following two methods areconsidered.

The first method is a method of further increasing the number of bitswhich can be displayed. In other words, display is performed with not 6bits but 7 bits or more, and preferably 8 bits or more. As a result, asmooth image can be displayed even in the low gray scale region.

The second method is a method of displaying a smooth image by notsatisfying γ=2.2 in the low gray scale region but by linearly changingthe luminance. FIG. 30 shows a selection method of a subpixel and asubframe in this case. In FIG. 30, gray scale levels up to a gray scalelevel of 17 in the 5-bit gray scale are the same as those in the 6-bitgray scale. However, at a gray scale level of 18 in the 5-bit gray scalewith gamma correction, lighting is actually performed by a selectionmethod of a subpixel and a subframe at a gray scale level of 19 in the6-bit gray scale. Similarly, at a gray scale level of 19 in the 5-bitgray scale with gamma correction, display is actually performed by aselection method of a subpixel and a subframe at a gray scale level of21 in the 6-bit gray scale, and at a gray scale level of 20 in the 5-bitgray scale with gamma correction, display is actually performed by aselection method of a subpixel and a subframe at a gray scale level of24 in the 6-bit gray scale. Here, FIGS. 31A and 31B are graphs of thegray scale level x and the luminance y. FIG. 31A shows the relationbetween the gray scale level x and the luminance y at all the gray scalelevels, while FIG. 31B shows the relation between the gray scale level xand the luminance y in the low gray scale region. In the low gray scaleregion, the luminance changes linearly. By performing such gammacorrection, a smoother image can be displayed in the low gray scaleregion.

That is, the luminance is changed in linear proportion to the grayscales in the low gray scale region, while the luminance is changed innonlinear proportion to the gray scale levels in the other gray scaleregion; thus, a smoother image can be displayed in the low gray scaleregion.

Note that the correspondence table between the 5-bit gray scale levelswith gamma correction and the 6-bit gray scale levels may be changed asappropriate. Thus, by changing the correspondence table, the degree ofgamma correction (i.e., the value of γ) can be easily changed.Accordingly, the invention is not limited to γ=2.2.

Further, the number of bits (e.g., p bits where p is an integer) set tobe displayed and the number of bits (e.g., q bits where q is an integer)with gamma correction to be displayed are not particularly limitedthereto. When display is performed with gamma correction, the number ofbits p is preferably set as large as possible in order to express grayscales smoothly. However, if the number of bits p is set too large, aproblem may arise such that the number of subframes becomes too large.Thus, the relation between the number of bits q and p preferablysatisfies q+2≦p≦q+5. Accordingly, gray scales can be smoothly expressedwhile suppressing the number of subframes.

In this manner, by performing gamma correction using the methoddescribed in this embodiment mode, an image with higher image qualitycan be displayed.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in Embodiment Mode1.

Embodiment Mode 3

In Embodiment Mode 1, the overlapping time gray scale method is appliedto subframes of which light emission intensity is the same in eachsubpixel; however, the invention is not limited thereto. In thisembodiment mode, a case is described, in which the overlapping time grayscale method is applied to all subframes in each subpixel.

In this embodiment mode, a case is described, in which one pixel isdivided into two subpixels (SP1 and SP2) each having the same area; andone frame is divided into eight subframes (SF1 to SF8) each having thesame lighting period. FIG. 32 shows a selection method of a subpixel anda subframe in this case.

Here, the subpixels have the following areas: SP1=SP2=1, and thesubframes have the following lighting periods:SF1=SF2=SF3=SF4=SF5=SF6=SF7=SF8=1.

In FIG. 32, since the area of each subpixel is the same and the lightingperiod of each subframe is the same, light emission intensity is equalin all the subpixels and in all the subframes. Specifically, since thearea of each subpixel is 1 and the lighting period of each subframe is1, light emission intensity is 1×1=1.

Note that in each subpixel, the overlapping time gray scale method isapplied to all subpixels in each subframe. That is, the number oflighting subframes is continuously increased in accordance with increasein gray scale level, and a lighting subframe in a low gray scale levelis kept to be used for lighting in a high gray scale level.

In the example shown in FIG. 32, SP1 is always lit in SF1 when a grayscale at a gray scale level of 1 or more is expressed, always lit in SF2when a gray scale of 3 or more is expressed, always lit in SF3 when agray scale of 5 or more is expressed, always lit in SF4 when a grayscale of 7 or more is expressed, always lit in SF5 when a gray scale of9 or more is expressed, always lit in SF6 when a gray scale of 11 ormore is expressed, always lit in SF7 when a gray scale of 13 or more isexpressed, and always lit in SF8 when a gray scale of 15 or more isexpressed. SP2 is similar thereto.

As described above, each subpixel to be lit in each subframe isselected, so that 17 gray scales can be expressed.

By using a driving method shown in FIG. 32, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 7 and the pixel Bdisplays an image at a gray scale level of 8 by using the selectionmethod of the subpixel and the subframe shown in FIG. 32. FIG. 33 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 4 (=1+1+1+1), and the gray scale levelis sometimes perceived as 5 (=1+1+1+1+1) depending on a movement of theline of sight. Although the gray scale level is supposed to be perceivedas 7 and 8, the gray scale level is perceived to be 4 or 5, and therebya pseudo contour occurs. However, a gray scale gap is reduced ascompared with the conventional driving method; thus, a pseudo contour isreduced.

Note that more gray scales may be expressed by using image processingtechnology such as error diffusion or dither diffusion.

Note that although the area of each subpixel is the same and thelighting period of each subframe is the same in FIG. 32, the inventionis not limited thereto.

A case is described as an example, in which one pixel is divided intotwo subpixels (SP1 and SP2) so that an area ratio of subpixels is 1:2;and one frame is divided into eight subframes (SF1 to SF8) each havingthe same lighting period. FIG. 34 shows a selection method of a subpixeland a subframe in this case.

Here, the subpixels have the following areas: SP1=1 and SP2=2, and thesubframes have the following lighting periods:SF1=SF2=SF3=SF4=SF5=SF6=SF7=SF8=1.

Note that in each subpixel, the overlapping time gray scale method isapplied to all subpixels in each subframe. That is, the number oflighting subframes is continuously increased in accordance with increasein gray scale level, and a lighting subframe in a low gray scale levelis kept to be used for lighting in a high gray scale level.

In the example shown in FIG. 34, SP1 is always lit in SF1 when a grayscale at a gray scale level of 1 or more is expressed, always lit in SF2when a gray scale at a gray scale level of 4 or more is expressed,always lit in SF3 when a gray scale at a gray scale level of 7 or moreis expressed, always lit in SF4 when a gray scale at a gray scale levelof 10 or more is expressed, always lit in SF5 when a gray scale at agray scale level of 13 or more is expressed, always lit in SF6 when agray scale at a gray scale level of 16 or more is expressed, always litin SF7 when a gray scale at a gray scale level of 19 or more isexpressed, and always lit in SF8 when a gray scale at a gray scale levelof 22 or more is expressed. SP2 is similar thereto.

As described above, each subpixel to be lit in each subframe isselected, so that 17 gray scales among gray scale levels of 0 to 24 canbe expressed. Note that the other gray scales among the gray scalelevels of 0 to 24, which cannot be expressed, are expressed by usingimage processing technology such as error diffusion or dither diffusion.Thus, 25e gray scales at the gray scale levels of 0 to 24 can beexpressed.

By using a driving method shown in FIG. 34, a pseudo contour can bereduced as compared with the conventional driving method. For example,the pixel A displays an image at a gray scale level of 15 and the pixelB displays an image at a gray scale level of 16 by using the selectionmethod of the subpixel and the subframe shown in FIG. 34. FIG. 35 showsa lighting or non-lighting state of each subpixel in each subframe inthis case. For example, when a line of sight is moved, a gray scalelevel is sometimes perceived as 10 (=2+2+2+1+1+2), and the gray scalelevel is sometimes perceived as 11 (=1+2+2+2+2+1+1) depending on amovement of the line of sight. Although the gray scale level is supposedto be perceived as 15 and 16, the gray scale level is perceived to be 10or 11, and thereby a pseudo contour occurs. However, a gray scale gap isreduced as compared with the conventional driving method; thus, a pseudocontour is reduced.

Note that more gray scales may be expressed by using image processingtechnology such as error diffusion or dither diffusion.

As another example, a case is described, in which one pixel is dividedinto two subpixels (SP1 and SP2) so that an area ratio of the subpixelsis 1:2; one frame is divided into three subframes (SF1, SF2, and SF3) sothat a ratio of lighting period between the subframes is 1:4:16; andfurther, two subframes of the three subframe (SF1 to SF3) are dividedinto a plurality of subframes. FIG. 36 shows a selection method of asubpixel and a subframe in this case. In FIG. 36, SF2 and SF3 aresubframes to be divided into a plurality of subframes.

Here, the subpixels have the following areas: SP1=1 and SP2=2, and thesubframes have the following lighting periods: SF1=1, SF2=4, and SF3=16.

FIG. 36 shows a case where SF2 is divided into two subframes and SF3 isdivided into four subframes. For example, SF2 having a lighting periodof 4 is divided into two subframes SF21 and SF22 each having a lightingperiod of 2. SF3 having a lighting period of 16 is divided into foursubframes SF31, SF32, SF33, and SF34 each having a lighting period of 4.

Thus, one frame is divided into seven subframes, and the lighting periodof each subframe is SF1=1, SF21=2, SF22=2, SF31=4, SF32=4, SF33=4, andSF34=4.

Note that in each subpixel, the overlapping time gray scale method isapplied to all subpixels in each subframe. That is, the number oflighting subframes is continuously increased in accordance with increasein gray scale level, and a lighting subframe in a low gray scale levelis kept to be used for lighting in a high gray scale level.

In the example shown in FIG. 36, SP1 is always lit in SF1 when a grayscale at a gray scale level of 1 or more is expressed, always lit inSF21 when a gray scale at a gray scale level of 5 or more is expressed,always lit in SF22 when a gray scale at a gray scale level of 11 or moreis expressed, always lit in SF31 when a gray scale at a gray scale levelof 19 or more is expressed, always lit in SF32 when a gray scale at agray scale level of 31 or more is expressed, always lit in SF33 when agray scale at a gray scale level of 43 or more is expressed, and alwayslit in SF34 when a gray scale at a gray scale level of 55 or more isexpressed. SP2 is similar thereto.

As described above, each subpixel to be lit in each subframe isselected, so that 17 gray scales among gray scale levels of 0 to 63 canbe expressed. Note that the other gray scales among the gray scalelevels of 0 to 63, which cannot be expressed, are expressed by usingimage processing technology such as error diffusion or dither diffusion.Thus, 64 gray scales at the gray scale levels of 0 to 63 can beexpressed.

Note that more gray scales may be expressed by using image processingtechnology such as error diffusion or dither diffusion.

Thus, a pseudo contour can be reduced as compared with the conventionaldriving method by using the driving method in this embodiment mode.

As the examples shown in FIGS. 32 and 34, when the length of lightingperiods of all subframes is the same, an erasing operation is notnecessary to be performed on the all subframes; thus, power consumed foran erasing operation can be eliminated. Further, a duty ratio can beimproved, and luminance can be improved. By improvement in duty ratio, avoltage applied to the light emitting element can be reduced. Therefore,power consumption can be reduced and deterioration of the light emittingelement can be suppressed.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 and 2.

Embodiment Mode 4

In this embodiment mode, an operation of a display device of theinvention is described with reference to the timing charts.

In this embodiment mode, a case is described as an example, in which onepixel is divided into two subpixels (SP1 and SP2) so that an area ratioof the subpixels is 1:2; one frame is divided into three subframes (SF1,SF2, and SF3) so that a ratio of lighting period between the subframesis 1:4:16; and further, one subframe of the three subframes (SF1 to SF3)is divided into two subframes. As a specific example, a case of usingthe selection method of the subpixel and the subframe shown in FIG. 1 isdescribed.

FIG. 37 is a timing chart in a case where a period for writing a signalto a pixel and a lighting period are separated.

Note that a timing chart shows timing of light emission of a pixel inone frame; and the horizontal direction of FIG. 37 indicates time, andthe vertical direction thereof indicates a row in which pixels arearranged.

First, signals for one screen are input to all pixels in a signalwriting period. During this period, the pixels are not lit. After thesignal writing period, a lighting period starts and the pixels are lit.The length of the lighting period at this time is 1. Next, a subsequentsubframe starts and signals for one screen are input to all the pixelsin the signal writing period. During this period, the pixels are notlit. After the signal writing period, the lighting period starts and thepixels are lit. The length of the lighting period at this time is 4.

By repeating similar operations, the length of the lighting periods isarranged in order of 1, 4, 8, and 8.

Such a driving method where a period for writing a signal to a pixel anda lighting period are separated is preferably applied to a plasmadisplay. Note that when the driving method is used for a plasma display,an initialization operation or the like is necessary, which is omittedin FIG. 37 for simplicity.

In addition, this driving method is also preferably applied to an ELdisplay (e.g. an organic EL display, an inorganic EL display, or adisplay formed of elements including an inorganic substance and anorganic substance), a field emission display, a display using a digitalmicromirror device (DMD), and the like.

FIG. 38 shows a pixel configuration for realizing the driving method inwhich a period for writing a signal to a pixel and a lighting period areseparated. Note that in FIG. 38, the number of light emitting elementsindicates the area of each pixel. Therefore, one light emitting elementis provided in the subpixel 1 (SP1) and two light emitting elements areprovided in the subpixel 2 (SP2).

First, the pixel configuration shown in FIG. 38 is described. SP1includes a first selection transistor 3811, a first driving transistor3813, a first storage capacitor 3812, a signal line 3815, a first powersupply line 3816, a first scan line 3817, a first light emitting element3814, and a second power supply line 3818.

A gate electrode of the first selection transistor 3811 is connected tothe first scan line 3817, a first electrode thereof is connected to thesignal line 3815, and a second electrode thereof is connected to asecond electrode of the first storage capacitor 3812 and a gateelectrode of the first driving transistor 3813. A first electrode of thefirst storage capacitor 3812 is connected to the first power supply line3816. A first electrode of the first driving transistor 3813 isconnected to the first power supply line 3816, and a second electrodethereof is connected to a first electrode of the first light emittingelement 3814. A second electrode of the first light emitting element3814 is connected to the second power supply line 3818.

SP2 includes a second selection transistor 3821, a second drivingtransistor 3823, a second storage capacitor 3822, the signal line 3815,the first power supply line 3816, a second scan line 3827, a secondlight emitting element 3824, and a third power supply line 3828. Notethat connections of each element and each wiring in SP2 are similar tothose in SP1; therefore, description thereof is omitted.

Next, an operation of the pixel shown in FIG. 38 is described. Here, anoperation of SP1 is described. By increasing a potential of the firstscan line 3817, the first scan line 3817 is selected, the firstselection transistor 3811 is turned on, and a signal is input from thesignal line 3815 to the first storage capacitor 3812. Thus, a current ofthe first driving transistor 3813 is controlled in accordance with thesignal, and a current flows from the first power supply line 3816 to thefirst light emitting element 3814. Note that an operation of SP2 issimilar to that of SP1; therefore, description thereof is omitted.

In this case, the number of light emitting elements to emit light ischanged depending on which scan line of the first and second scan linesis selected. For example, when only the first scan line 3817 isselected, only the first selection transistor 3811 is turned on, andonly the current of the first driving transistor 3813 is controlled;thus, only the first light emitting element 3814 emits light. That is,only SP1 emits light. On the other hand, when only the second scan line3827 is selected, only the second selection transistor 3821 is turnedon, and only a current of the second driving transistor 3823 iscontrolled; thus, only the second light emitting element 3824 emitslight. That is, only SP2 emits light. Further, when both the first andsecond scan lines 3817 and 3827 are selected, the first and secondselection transistors 3811 and 3821 are turned on, and the currents ofthe first and second driving transistors 3813 and 3823 is controlled;thus, both the first and second light emitting elements 3814 and 3824emit light. That is, both SP1 and SP2 emit light.

Note that in the signal writing period, potentials of the second andthird power supply lines 3818 and 3828 are controlled so that a voltageis not applied to the light emitting elements 3814 and 3824. Forexample, in a case of SP1, the second power supply line 3818 may be setin a floating state. Alternatively, the potential of the second powersupply line 3818 may be made lower than a potential of the signal line3815 by a threshold voltage of the first driving transistor 3813.Further alternatively, the potential of the second power supply line3818 may be made equal to or higher than that of the signal line 3815.As a result, the light emitting element 3814 can be prevented fromlighting in the signal writing period. Note that SP2 is similar thereto.

Note that the second power supply line 3818 and the third power supplyline 3828 may be either different wirings or the same wiring.

Note that when one pixel is divided into m subpixels (m is an integer ofm≦2), in order to realize the pixel configuration shown in FIG. 38, thenumber of scan lines included in one pixel may be 2 or more and m orless, and a selection transistor included in at least one subpixel amongthe m subpixels may be connected to a scan line different from thatconnected to a selection transistor included in another subpixel.

FIG. 38 shows a configuration example in a case where a plurality ofscan lines is provided, and the number of light emitting elements toemit light is changed by controlling which scan line is selected, andthereby a gray scale is expressed. It is also possible that a pluralityof signal lines is provided, and the number of light emitting elementsto emit light is changed by controlling what kind of signal is input towhich signal line, and thereby a gray scale is expressed. FIG. 39 showsa configuration example of the this case.

First, a pixel configuration shown in FIG. 39 is described. SP1 includesa first selection transistor 3911, a first driving transistor 3913, afirst storage capacitor 3912, a first signal line 3915, a first powersupply line 3916, a scan line 3917, a first light emitting element 3914,and a second power supply line 3918.

A gate electrode of the first selection transistor 3911 is connected tothe scan line 3917, a first electrode thereof is connected to the firstsignal line 3915, and a second electrode thereof is connected to the asecond electrode of the first storage capacitor 3912 and a gateelectrode of the first driving transistor 3913. A first electrode of thefirst storage capacitor 3912 is connected to the first power supply line3916. A first electrode of the first driving transistor 3913 isconnected to the first power supply line 3916, and a second electrodethereof is connected to a first electrode of the first light emittingelement 3914. A second electrode of the first light emitting element3914 is connected to the second power supply line 3918.

SP2 includes a second selection transistor 3921, a second drivingtransistor 3923, a second storage capacitor 3922, a second signal line3925, the first power supply line 3916, the scan line 3917, a secondlight emitting element 3924, and a third power supply line 3928. Notethat connections of each element and each wiring in SP2 are similar tothose in SP1; therefore, description thereof is omitted.

Next, an operation of the pixel shown in FIG. 39 is described. Here, anoperation of SP1 is described. By increasing a potential of the scanline 3917, the scan line 3917 is selected, the first selectiontransistor 3911 is turned on, and a video signal is input from the firstsignal line 3915 to the first storage capacitor 3912. Thus, a current ofthe first driving transistor 3913 is controlled in accordance with thevideo signal, and a current flows from the first power supply line 3916to the first light emitting element 3914. Note that an operation of SP2is similar to that of SP1; therefore, description thereof is omitted.

In this case, the number of light emitting elements to emit light ischanged in accordance with the video signals input to the first andsecond signal lines. For example, when a low-level signal is input tothe first signal line 3915 and a high-level signal is input to thesecond signal line 3925, only the first driving transistor 3913 isturned on; thus, only the first light emitting element 3914 emits light.That is, only SP1 emits light. On the other hand, when a high-levelsignal is input to the first signal line 3915 and a low-level signal isinput to the second signal line 3925, only the second driving transistor3923 is turned on; thus, only the second light emitting element 3924emits light. That is, only SP2 emits light. Further, when low-levelsignals are input to the first and second signal lines 3915 and 3925,both the first and second driving transistors 3913 and 3923 are turnedon; thus, both the first and second light emitting elements 3914 and3924 emit light. That is, both SP1 and SP2 emit light.

The currents flowing to the first and second light emitting elements3914 and 3924 can be controlled by controlling voltages of the videosignals input to the first and second signal lines 3915 and 3925. As aresult, luminance of each subpixel can be changed, and a gray scale canbe expressed. For example, when SP1 with the area of 1 is lit in SF1having a lighting period of 1, light emission intensity is 1; however,when a voltage level of the video signal input to the first signal line3915 is changed, luminance of the first light emitting element 3914 canbe changed. Thus, gray scales much more than those which can beexpressed by using the area of the subpixel and the length of thelighting period of the subframe can be expressed. Further, by expressinga gray scale by a voltage applied to the light emitting element includedin each subpixel in addition to the area of the subpixel and the lengthof the lighting period of the subframe, the number of subpixels andsubframes necessary to express the same gray scale can be reduced. Thus,an aperture ratio of a pixel portion can be increased. In addition, aduty ratio can be improved, and luminance can be improved. Byimprovement in duty ratio, a voltage applied to the light emittingelement can be reduced. Therefore, power consumption can be reduced anddeterioration of the light emitting element can be suppressed.

Note that when one pixel is divided into m subpixels (m is an integer ofm≦2), in order to realize the pixel configuration shown in FIG. 39, thenumber of signal lines included in one pixel may be 2 or more and m orless, and a selection transistor included in at least one subpixel amongthe m subpixels may be connected to a signal line different from thatconnected to a selection transistor included in another subpixel.

Note that a common power supply line (each of the first power supplylines 3816 and 3916) is connected to each subpixel in FIGS. 38 and 39;however, a plurality of power supply lines corresponding to the firstpower supply line in each of FIGS. 38 and 39 may be provided, and apower supply voltage applied to the subpixel may be changed. FIG. 40shows a configuration example in a case where two power supply linescorresponding to the first power supply line in FIG. 38 are provided.

First, a pixel configuration shown in FIG. 40 is described. SP1 includesa first selection transistor 4011, a first driving transistor 4013, afirst storage capacitor 4012, a signal line 4015, a first power supplyline 4016, a first scan line 4017, a first light emitting element 4014,and a second power supply line 4018.

A gate electrode of the first selection transistor 4011 is connected tothe first scan line 4017, a first electrode thereof is connected to thesignal line 4015, and a second electrode thereof is connected to asecond electrode of the first storage capacitor 4012 and a gateelectrode of the first driving transistor 4013. A first electrode of thefirst storage capacitor 4012 is connected to the first power supply line4016. A first electrode of the first driving transistor 4013 isconnected to the first power supply line 4016, and a second electrodethereof is connected to a first electrode of the first light emittingelement 4014. A second electrode of the first light emitting element4014 is connected to the second power supply line 4018.

SP2 includes a second selection transistor 4021, a second drivingtransistor 4023, a second storage capacitor 4022, the signal line 4015,a second scan line 4027, a second light emitting element 4024, a thirdpower supply line 4028, and a fourth power supply line 4026. Note thatconnections of each element and each wiring in SP2 are similar to thosein SP1; therefore, description thereof is omitted.

Currents flowing to the first and second light emitting elements 4014and 4024 can be controlled by controlling voltages applied to the firstand fourth power supply lines 4016 and 4026. As a result, luminance ofeach subpixel can be changed, and a gray scale can be expressed. Forexample, when SP1 with the area of 1 is lit in SF1 having a lightingperiod of 1, light emission intensity is 1; however, when a voltagelevel applied to the first power supply line 4016 is changed, luminanceof the first light emitting element 4014 can be changed. Thus, grayscales much more than those which can be expressed by using the area ofthe subpixel and the length of the lighting period of the subframe canbe expressed. Further, by expressing a gray scale by a voltage appliedto the light emitting element included in each subpixel in addition tothe area of the subpixel and the length of the lighting period of thesubframe, the number of subpixels and subframes necessary to express thesame gray scale can be reduced. Thus, an aperture ratio of a pixelportion can be increased. In addition, a duty ratio can be improved, andluminance can be improved. By improvement in duty ratio, a voltageapplied to the light emitting element can be reduced. Therefore, powerconsumption can be reduced and deterioration of the light emittingelement can be suppressed.

Note that when one pixel is divided into m subpixels (m is an integer ofm≦2), in order to realize the pixel configuration shown in FIG. 40, thenumber of power supply lines, which correspond to the first power supplyline in FIG. 38 or 39, included in one pixel may be 2 or more and m orless, and a selection transistor included in at least one subpixel amongthe m subpixels may be connected to the power supply line different fromthat connected to a selection transistor included in another subpixel.

Next, FIG. 41 shows a timing chart in a case where a period for writinga signal to a pixel and a lighting period are not separated. In eachrow, immediately after each signal is written, a lighting period starts.

In a certain row, after each signal is written and a predeterminedlighting period is finished, a signal writing operation starts in asubsequent subframe. By repeating such operations, the length of thelighting periods is arranged in order of 1, 4, 8, and 8.

In such a manner, a plurality of subframes can be arranged in one frameeven when signal writing operation is slow.

Such a driving method is preferably applied to a plasma display. Notethat when the driving method is used for a plasma display, aninitialization operation or the like is necessary, which is omitted inFIG. 41 for simplicity.

In addition, this driving method is also preferably applied to an ELdisplay, a field emission display, a display using a digital micromirrordevice (DMD), and the like.

FIG. 42 shows a pixel configuration for realizing the driving method inwhich a period for writing a signal to a pixel and a lighting period arenot separated. Note that in order to realize such a driving method, aplurality of rows is necessary to be able to be selected at the sametime.

First, a pixel configuration shown in FIG. 42 is described. SP1 includesa first selection transistor 4211, a second selection transistor 4221, afirst driving transistor 4213, a first storage capacitor 4212, a firstsignal line 4215, a second signal line 4225, a first power supply line4216, a first scan line 4217, a second scan line 4227, a first lightemitting element 4214, and a second power supply line 4218.

A gate electrode of the first selection transistor 4211 is connected tothe first scan line 4217, a first electrode thereof is connected to thefirst signal line 4215, and a second electrode thereof is connected to asecond electrode of the second selection transistor 4221, a secondelectrode of the first storage capacitor 4212, and a gate electrode ofthe first driving transistor 4213. A gate electrode of the secondselection transistor 4221 is connected to the second scan line 4227, anda first electrode thereof is connected to the second signal line 4225. Afirst electrode of the first storage capacitor 4212 is connected to thefirst power supply line 4216. A first electrode of the first drivingtransistor 4213 is connected to the first power supply line 4216, and asecond electrode thereof is connected to a first electrode of the firstlight emitting element 4214. A second electrode of the first lightemitting element 4214 is connected to the second power supply line 4218.

SP2 includes a third selection transistor 4231, a fourth selectiontransistor 4241, a second driving transistor 4223, a second storagecapacitor 4222, the first signal line 4215, the second signal line 4225,the first power supply line 4216, a third scan line 4237, a fourth scanline 4247, a second light emitting element 4224, and a third powersupply line 4228. Note that connections of each element and each wiringin SP2 are similar to those in SP1; therefore, description thereof isomitted.

Next, an operation of the pixel shown in FIG. 42 is described. Here, anoperation of SP1 is described. By increasing a potential of the firstscan line 4217, the first scan line 4217 is selected, the firstselection transistor 4211 is turned on, and a signal is input from thefirst signal line 4215 to the first storage capacitor 4212. Thus, acurrent of the first driving transistor 4213 is controlled in accordancewith the signal, and a current flows from the first power supply line4216 to the first light emitting element 4214. Similarly, by increasinga potential of the second scan line 4227, the second scan line 4227 isselected, the second selection transistor 4221 is turned on, and asignal is input from the second signal line 4225 to the first storagecapacitor 4212. Thus, the current of the first driving transistor 4213is controlled in accordance with the signal, and a current flows fromthe first power supply line 4216 to the first light emitting element4214. Note that an operation of SP2 is similar to that of SP1;therefore, description thereof is omitted.

The first scan line 4217 and the second scan line 4227 can be separatelycontrolled. Similarly, the third scan line 4237 and the fourth scan line4247 can be separately controlled. Further, the first signal line 4215and the second signal line 4225 can be separately controlled. Thus,signals can be input to pixels of two rows at the same time, and therebythe driving method shown in FIG. 41 can be realized.

The driving method shown in FIG. 41 can also be realized by using thepixel configuration of FIG. 38. In this case, a method where one gateselection period is divided into a plurality of subgate selectionperiods is used. First, as shown in FIG. 41, one gate selection periodis divided into a plurality of (two in FIG. 43) subgate selectionperiods. Then, each scan line is selected by increasing a potential ofeach scan line, and a corresponding signal is input to the signal line3815. For example, in one gate selection period, the i-th row isselected in the first half of the subgate selection period, and the j-throw is selected in the latter half of the subgate selection period.Thus, the operation can be performed as if the two rows are selected atthe same time in one gate selection period.

Note that details of such a driving method are described in, forexample, Japanese Published Patent Application No. 2001-324958 and thelike, which can be applied in combination with this application.

Note that FIG. 42 shows an example where a plurality of scan lines isprovided; however, one signal line may be provided and first electrodesof the first to fourth selection transistors may be connected to thesignal line. Further, a plurality of power supply lines corresponding tothe first power supply line in FIG. 42 may be provided.

Next, FIG. 44 shows a timing chart in a case where an operation oferasing a signal of a pixel is performed. In each row, signal writingoperation is performed, and the signal of each pixel is erased before asubsequent signal writing operation. Thus, the length of a lightingperiod can be easily controlled.

In a certain row, after each signal is written and a predeterminedlighting period is finished, a signal writing operation starts in asubsequent subframe. If the lighting period is short, a signal erasingoperation is performed to forcibly provide a non-lighting state. Byrepeating such operations, the length of the lighting periods isarranged in order of 1, 4, 8, and 8.

Note that the signal erasing operation is performed in the lightingperiods of 1 and 4 in FIG. 44; however, the invention is not limitedthereto. The erasing operation may be performed in another lightingperiod.

In such a manner, a plurality of subframes can be arranged in one frameeven when a signal writing operation is slow. Further, in a case wherethe erasing operation is performed, data for erasing is not necessary tobe obtained as well as a video signal; thus, the driving frequency of asignal line driver circuit can also be reduced.

Such a driving method is preferably applied to a plasma display. Notethat when the driving method is used for a plasma display, aninitialization operation or the like is necessary, which is omitted inFIG. 44 for simplicity.

In addition, this driving method is also preferably applied to an ELdisplay, a field emission display, a display using a digital micromirrordevice (DMD), and the like.

FIG. 45 shows a pixel configuration in a case where the erasingoperation is performed. A pixel shown in FIG. 45 is a configurationexample in a case where the erasing operation is performed by using anerasing transistor.

First, the pixel configuration shown in FIG. 45 is described. SP1includes a first selection transistor 4511, a first driving transistor4513, a first erasing transistor 4519, a first storage capacitor 4512, asignal line 4515, a first power supply line 4516, a first scan line4517, a second scan line 4527, a first light emitting element 4514, anda second power supply line 4518.

A gate electrode of the first selection transistor 4511 is connected tothe first scan line 4517, a first electrode thereof is connected to thesignal line 4515, and a second electrode thereof is connected to asecond electrode of the first erasing transistor 4519, a secondelectrode of the first storage capacitor 4512, and a gate electrode ofthe first driving transistor 4513. A gate electrode of the first erasingtransistor 4519 is connected to the second scan line 4527, and a firstelectrode thereof is connected to the first power supply line 4516. Afirst electrode of the first storage capacitor 4512 is connected to thefirst power supply line 4516. A first electrode of the first drivingtransistor 4513 is connected to the first power supply line 4516, and asecond electrode thereof is connected to a first electrode of the firstlight emitting element 4514. A second electrode of the first lightemitting element 4514 is connected to the second power supply line 4518.

SP2 includes a second selection transistor 4521, a second drivingtransistor 4523, a second erasing transistor 4529, a second storagecapacitor 4522, the signal line 4515, the first power supply line 4516,a third scan line 4537, a fourth scan line 4547, a second light emittingelement 4524, and a third power supply line 4528. Note that connectionsof each element and each wiring in SP2 are similar to those in SP1;therefore, description thereof is omitted.

Next, an operation of the pixel shown in FIG. 45 is described. Here, anoperation of SP1 is described. By increasing a potential of the firstscan line 4517, the first scan line 4517 is selected, the firstselection transistor 4511 is turned on, and a signal is input from thesignal line 4515 to the first storage capacitor 4512. Thus, a current ofthe first driving transistor 4513 is controlled in accordance with thesignal, and a current flows from the first power supply line 4516 to thefirst light emitting element 4514.

In order to erase a signal, by increasing a potential of the second scanline 4527, the second scan line 4527 is selected, the first erasingtransistor 4519 is turned on, and the first driving transistor 4513 isturned off. Thus, no current flows to the first light emitting element4514. As a result, a non-lighting period can be provided, and the lengthof the lighting period can be freely controlled.

Note that an operation of SP2 is similar to that of SP1; therefore,description thereof is omitted.

Although the erasing operation is performed by using the erasingtransistors 4519 and 4529 in FIG. 45, another method can also be used aslong as a non-lighting period is forcibly provided so that no currentflows to the light emitting elements 4514 and 4524. Accordingly, aswitch may be provided in a path where a current flows from the firstpower supply line 4516 to the second and third power supply lines 4518and 4528 through the light emitting elements 4514 and 4524, and on/offof the switch may be controlled to provide a non-lighting period.Alternatively, a gate-source voltage of each of the driving transistors4513 and 4523 may be controlled to forcibly turn off the drivingtransistor.

FIG. 46 shows an example of a pixel configuration in a case where adriving transistor is forcibly turned off. A pixel shown in FIG. 46 is aconfiguration example in a case where a driving transistor is forciblyturned off by using an erasing diode.

First, the pixel configuration shown in FIG. 46 is described. SP1includes a first selection transistor 4611, a first driving transistor4613, a first storage capacitor 4612, a signal line 4615, a first powersupply line 4616, a first scan line 4617, a second scan line 4627, afirst light emitting element 4614, a second power supply line 4618, anda first erasing diode 4619.

A gate electrode of the first selection transistor 4611 is connected tothe first scan line 4617, a first electrode thereof is connected to thesignal line 4615, and a second electrode thereof is connected to asecond electrode of the first erasing diode 4619, a second electrode ofthe first storage capacitor 4612, and a gate electrode of the firstdriving transistor 4613. A first electrode of the first erasing diode4619 is connected to the second scan line 4627. A first electrode of thefirst storage capacitor 4612 is connected to the first power supply line4616. A first electrode of the first driving transistor 4613 isconnected to the first power supply line 4616, and a second electrodethereof is connected to a first electrode of the first light emittingelement 4614. A second electrode of the first light emitting element4614 is connected to the second power supply line 4618.

SP2 includes a second selection transistor 4621, a second drivingtransistor 4623, a second storage capacitor 4622, the signal line 4615,the first power supply line 4616, a third scan line 4637, a fourth scanline 4647, a second light emitting element 4624, a third power supplyline 4628, and a second erasing diode 4629. Note that connections ofeach element and each wiring in SP2 are similar to those in SP1;therefore, description thereof is omitted.

Next, an operation of the pixel shown in FIG. 46 is described. Here, anoperation of SP1 is described. BY increasing a potential of the firstscan line 4617, the first scan line 4617 is selected, the firstselection transistor 4611 is turned on, and a signal is input from thesignal line 4615 to the first storage capacitor 4612. Thus, a current ofthe first driving transistor 4613 is controlled in accordance with thesignal, and a current flows from the first power supply line 4616 to thefirst light emitting element 4614.

In order to erase a signal, by increasing a potential of the second scanline 4627, the second scan line 4627 is selected, the first erasingdiode 4619 is turned on, and a current is made to flow from the secondscan line 4627 to the gate electrode of the first driving transistor4613. Accordingly, the first driving transistor 4613 is turned off.Thus, no current flows from the first power supply line 4616 to thefirst light emitting element 4614. As a result, a non-lighting periodcan be provided, and the length of the lighting period can be freelycontrolled.

In order to hold a signal, the potential of the second scan line 4627 isdecreased so that the second scan line 4627 is not selected. Thus, thefirst erasing diode 4619 is turned off, and a gate potential of thefirst driving transistor 4613 is held.

Note that an operation of SP2 is similar to that in SP1; therefore,description thereof is omitted.

Note that the erasing diodes 4619 and 4629 may be any element as long asa rectifying property is provided. The erasing diode may be a PN diode,a PIN diode, a Schottky diode, or a zener diode.

Alternatively, a diode-connected transistor (a gate and a drain thereofare connected) may be used. FIG. 47 is a circuit diagram of this case.As the first and second erasing diodes 4619 and 4629, diode-connectedtransistors 4719 and 4729 are used. Although n-channel transistors areused as the diode-connected transistors in FIG. 47, the invention is notlimited thereto and a p-channel transistor may also be used.

As another method, the driving method such as shown in FIG. 44 can berealized by using the pixel configuration of FIG. 38. In this case, amethod where one gate selection period is divided into a plurality ofsubgate selection periods is used. First, as shown in FIG. 43, one gateselection period is divided into a plurality of (two in FIG. 43) subgateselection periods. Then, each scan line is selected by increasing apotential of each scan line in each subgate selection period, and eachcorresponding signal (either a video signal or an erase signal) is inputto the signal line 3815. For example, when signals are input to pixelsin the i-th row and signals are erased from pixels in the j-th row, inone gate selection period; the i-th row is selected in the first half ofthe subgate selection period, and the j-th row is selected in the latterhalf of the subgate selection period. When the i-th row is selected,video signals to be input to the pixels in the i-th row are input to thesignal line 3815. On the other hand, when the j-th row is selected,signals for turning off each driving transistor of the pixels in thej-th row are input to the signal line 3815. Thus, the operation can beperformed as if the two rows are selected at the same time and thesignal writing operation and the signal erasing operation are performedin one gate selection period.

Note that details of such a driving method are described in, forexample, Japanese Published Patent Application No. 2001-324958 and thelike, which can be applied in combination with this application.

Note that FIGS. 45 to 47 show examples where a plurality of scan linesis provided; however, a plurality of signal lines may be provided, or aplurality of power supply lines corresponding to the first power supplyline in each of FIGS. 45 to 47 may be provided.

Note that the timing charts, the pixel configurations, and the drivingmethods shown in this embodiment mode are examples, and the invention isnot limited thereto. The invention can be applied to various timingcharts, pixel configurations, and driving methods. Further, in the pixelconfiguration shown in this embodiment mode, polarity of each transistoris not limited.

Note that in this embodiment mode, a lighting period, a signal writingperiod, and a non-lighting period are provided in one frame; however,the invention is not limited thereto and another operation period may beprovided. For example, a so-called reverse bias period, which is aperiod when a voltage having polarity opposite to normal polarity isapplied to a light emitting element, may be provided. By provision ofthe reverse bias period, reliability of the light emitting element isimproved in some cases.

Note that in the pixel configuration shown in this embodiment mode, astorage capacitor can be omitted by substituting parasitic capacitanceof a transistor.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 3.

Embodiment Mode 5

In this embodiment mode, a layout of a pixel in a display device of theinvention is described. As an example, FIG. 48 shows a layout diagram ofthe pixel configuration shown in FIG. 38. Note that reference numeralsused in FIG. 48 correspond to the reference numerals used in FIG. 38.Note that the invention is not limited to the layout of FIG. 48.

In the layout diagram shown in FIG. 48, the first and second selectiontransistors 3811 and 3821, the first and second driving transistors 3813and 3823, the first and second storage capacitors 3812 and 3822, anelectrode 3819 of the first light emitting element 3814, an electrode3829 of the second light emitting element 3824, the signal line 3815,the first power supply line 3816, and the first and second scan lines3817 and 3827 are provided. An area ratio of the electrode 3819 of thefirst light emitting element 3814 to the electrode 3829 of the secondlight emitting element 3824 is 1:2.

The signal line 3815 and the first power supply line 3816 are formed ofa second wiring. The first and second scan lines 3817 and 3827 areformed of a first wiring.

When a transistor has a top gate structure, films are formed in order ofa substrate, a semiconductor layer, a gate insulating film, a firstwiring, an interlayer insulating film, and a second wiring. When atransistor has a bottom gate structure, films are formed in order of asubstrate, a first wiring, a gate insulating film, a semiconductorlayer, an interlayer insulating film, and a second wiring.

Note that the first and second selection transistors 3811 and 3821, andthe first and second driving transistors 3813 and 3823 can have variousstructures. For example, a multi-gate structure may be used in which twoor more gate electrodes are provided. In a multi-gate structure, astructure is such that channel regions are connected in series;therefore, the structure is such that a plurality of transistors isconnected in series. FIG. 49 shows a layout diagram of the first andsecond driving transistors 3813 and 3823 having a multi-gate structure.By having a multi-gate structure, an off current can be reduced,reliability can be improved by improvement in withstand voltage of thetransistors, and the transistors can have flat characteristics even if adrain-source voltage changes when operating in a saturation region,since a drain-source current does not change much. Alternatively, thetransistors may have a structure where gate electrodes are provided overand under a channel. By having a structure where gate electrodes areprovided over and under a channel, the amount of current is increasedsince the number of channel regions is increased, and an S-value can bereduced since a depletion layer is easily formed. When gate electrodesare provided over and under a channel, the structure is such that aplurality of transistors is connected in parallel. Alternatively, thetransistor may have a structure where a gate electrode is provided overor under a channel; a forward staggered structure; a reverse staggeredstructure; or a structure where a channel region is divided into aplurality of regions and the divided regions may be connected inparallel or in series. Further alternatively, a source electrode or adrain electrode may overlap with the channel (or a part thereof). Byhaving a structure where a source electrode or a drain electrodeoverlaps with the channel (or a part thereof), an unstable operation dueto accumulation of electric charge in a part of the channel can beprevented. Further, an LDD region may be provided. By providing an LDDregion, an off current can be reduced, reliability can be improved byimprovement in withstand voltage of the transistors, and the transistorscan have flat characteristics even if a drain-source voltage changeswhen operating in a saturation region, since a drain-source current doesnot change much.

Note that a wiring and an electrode are formed to contain one or aplurality of elements selected from aluminum (Al), tantalum (Ta),titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium(Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu),magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb),silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga),indium (In), tin (Sn), and oxygen (O); a compound or an alloy materialcontaining one or a plurality of elements selected from the foregoinggroup (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium tinoxide to which silicon oxide is added (in this specification, referredto as ITSO), zinc oxide (ZnO), aluminum-neodymium (Al—Nd),magnesium-silver (Mg—Ag), or the like); a substance in which two or moreof these compounds are combined; or the like. Alternatively, a wiringand an electrode are formed to include a compound (silicide) of theaforementioned elements and silicon (e.g., aluminum-silicon,molybdenum-silicon, nickel-silicide, or the like), or a compound of theaforementioned elements and nitrogen (e.g., titanium nitride, tantalumnitride, molybdenum nitride, or the like). Note that silicon (Si) maycontain a large amount of n-type impurities (such as phosphorous) orp-type impurities (such as boron). By containing such impurities,conductivity can be improved and silicon can be easily used as a wiringor an electrode since it acts in a similar manner to a regularconductor. In addition, silicon may be single crystalline,polycrystalline (polysilicon), or amorphous (amorphous silicon). Byusing single crystalline silicon or polycrystalline silicon, resistancecan be decreased. By using amorphous silicon, a manufacturing processcan be simplified. Note that since aluminum and silver have highconductivity, signal delay can be reduced and microfabrication can beperformed since etching is easily performed. Since copper has highconductivity, signal delay can be reduced. Molybdenum is preferablesince it can be manufactured without causing defective materials even ifit is in contact with an oxide semiconductor such as ITO or IZO, orsilicon, and also, etching is easily performed, and molybdenum has highheat resistance. Note that titanium is preferable since titanium can bemanufactured without causing defective materials even if it is incontact with an oxide semiconductor such as ITO or IZO, or silicon, andit has high heat resistance. Further, tungsten and neodymium arepreferable since they have high heat resistance. In particular, an alloyof neodymium and aluminum is preferable since heat resistance isimproved and hillocks are not easily formed in aluminum. Silicon ispreferable since it can be formed at the same time as a semiconductorlayer included in a transistor, and it has high heat resistance. Notethat indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxideto which silicon oxide is added (ITS0), zinc oxide (ZnO), and silicon(Si) have light transmitting properties; therefore, they are preferablesince they can be used in a portion where light is transmitted. Forexample, they can be used for a pixel electrode and a common electrode.

Note that the aforementioned materials may have a single-layer structureor a stacked-layer structure to form a wiring and an electrode. Byforming a wiring and an electrode in a single-layer structure, amanufacturing process can be simplified, the number of days required forthe process can be reduced, and cost can be reduced. By having astacked-layer structure, a wiring and an electrode with good performancecan be formed by using the advantage and reducing the disadvantage ofeach material. For example, when a material with low resistance (such asaluminum) is included in a stacked-layer structure, low resistance of awiring can be realized. When a material having high heat resistance isincluded, for example, a stacked-layer structure is employed, in which amaterial having low heat resistance but having another advantage isinterposed between the materials having high heat resistance, andthereby, heat resistance of a wiring or an electrode as a whole can beincreased. For example, a stacked-layer structure where a layercontaining aluminum is interposed between layers containing molybdenumor titanium is preferable. Further, when there is a portion of thewiring or the electrode in direct contact with a wiring or an electrodeof a different material, the wirings or electrodes may adversely affecteach other. For example, if one material goes into the other materialand changes properties of the other material, an intended purpose isprevented from being achieved, or a problem which may inhibit normalmanufacturing is caused in some cases. In such a case, the problems canbe solved by interposing a certain layer between other layers or bycovering the certain layer with another layer. For example, in order tomake contact between indium tin oxide (ITO) and aluminum, it ispreferable to interpose titanium or molybdenum therebetween. Further, inorder to make contact between silicon and aluminum, it is preferable tointerpose titanium or molybdenum therebetween.

Note that the total light emission area of a pixel may be changed foreach pixel of R (red), G (green), and B (blue). FIG. 50 shows anembodiment of this case.

In an example shown in FIG. 50, each pixel includes two subpixels andalso includes a signal line 5015, a first power supply line 5016, andfirst and second scan lines 5017 and 5027. In FIG. 50, the size of thearea of each subpixel corresponds to a light emission area of eachsubpixel.

In FIG. 50, the order of the total light emission area of a pixel, fromlargest to smallest, is G, R, and B. Accordingly, appropriate colorbalance of R, G, and B can be realized; thus, it is possible to performcolor display with higher definition. Further, power consumption can bereduced, and the life of a light emitting element can be extended.

In addition, in a structure with R, G, B, and W (white) pixels, thenumber of subpixels in an RGB portion and the number of subpixels in a Wportion may be different. FIG. 51 shows an embodiment of this case.

In an example shown in FIG. 51, the RGB portion is divided into twosubpixels, and the W portion is divided into three subpixels. A signalline 5115, a first power supply line 5116, a first scan line 5117, asecond scan line 5127, and a third scan line 5137 are included.

As shown in FIG. 51, the number of subpixels in the RGB portion and thenumber of subpixels in the W portion are different; thus, it is possibleto perform white color display with higher definition.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 4.

Embodiment Mode 6

In this embodiment mode, structures and operations of a signal linedriver circuit, a scan line driver circuit, or the like in a displaydevice are described. In this embodiment mode, a case where one pixel isdivided into two subpixels (SP1, SP2) is described as an example.

First, a case where a period for writing a signal to a pixel and alighting period are separated is described. Here, a case of using thepixel configuration of FIG. 38 is described as an example. FIG. 52 showsa structure example of a display device in this case.

The display device shown in FIG. 52 includes a pixel portion 5201, firstand second scan line driver circuits 5202 and 5203, and a signal linedriver circuit 5204. The first scan line driver circuit 5202 and thefirst scan line 3817 are connected. The second scan line driver circuit5203 and the second scan line 3827 are connected. The signal line drivercircuit 5204 and the signal line 3815 are connected. Note that referencenumerals which denote the first and second scan lines and the signalline correspond to the reference numerals used in FIG. 38.

First, the scan line driver circuit is described. The first scan linedriver circuit 5202 sequentially outputs selection signals to the firstscan line 3817 connected to the subpixel 1 (SP1). The second scan linedriver circuit 5203 sequentially outputs selection signals to the secondscan line 3827 connected to the subpixel 2 (SP2). Thus, the selectionsignals are written to SP1 and SP2. Note that, in general, when onepixel is divided into m subpixels (m is an integer of m≧2), m scan linedriver circuits may be provided.

FIG. 53 shows a structure example of the first and second scan linedriver circuits 5202 and 5203. The scan line driver circuits 5202 and5203 each include a shift register 5301, an amplifier circuit 5302, andthe like.

Next, operations of the first and second scan line driver circuits 5202and 5203 shown in FIG. 53 are briefly described. A clock signal (G-CLK),a start pulse (G-SP), and a clock inverted signal (G-CLKB) are input tothe shift register 5301, and sampling pulses are sequentially output inaccordance with the timing of these signals. The output sampling pulsesare amplified by the amplifier circuit 5302 and input from each scanline to the pixel portion 5201.

Note that a buffer circuit or a level shifter circuit may be included inthe amplifier circuit 5302. Further, a pulse width control circuit andthe like may be included in the scan line driver circuit in addition tothe shift register 5301 and the amplifier circuit 5302.

Next, the signal line driver circuit is described. The signal linedriver circuit 5204 sequentially outputs video signals to the signalline 3815 connected to SP1 and SP2. The video signals output from thesignal line driver circuit 5204 are input to the pixel portion 5201. Animage is displayed in the pixel portion 5201 by control of a lightemitting state of a pixel in accordance with the video signals.

FIGS. 54A and 54B show a structure example of the signal line drivercircuit 5204. FIG. 54A shows an example of the signal line drivercircuit 5204 in a case where a signal is supplied to a pixel by linesequential driving. The signal line driver circuit 5204 in this casemainly includes a shift register 5401, a first latch circuit 5402, asecond latch circuit 5403, an amplifier circuit 5404, and the like. Notethat, the amplifier circuit 5404 may include a buffer circuit, a levelshifter circuit, a circuit having a function of converting a digitalsignal into an analog signal, or a circuit having a function ofperforming gamma correction.

Further, the pixel may include a circuit which outputs a current (avideo signal) to a light emitting element included in the pixel, inother words, a current source circuit.

Next, an operation of the signal line driver circuit 5204 shown in FIG.54A is briefly described. A clock signal (S-CLK), a start pulse (S-SP),and a clock inverted signal (S-CLKB) are input to the shift register5401, and sampling pulses are sequentially output in accordance with thetiming of these signals.

The sampling pulses output from the shift register 5401 are input to thefirst latch circuit 5402. A voltage V_(data) as a video signal is inputto the first latch circuit 5402 from a video signal line, and the videosignal is stored in each column in accordance with the timing of whenthe sampling pulses are input.

After storage of the video signal is completed to the last column in thefirst latch circuit 5402, a latch signal is input from a latch controlline in a horizontal retrace period, and the video signal stored in thefirst latch circuit 5402 is transferred to the second latch circuit 5403all at once. Thereafter, the video signals of one row, which have beenstored in the second latch circuit 5403, are input to the amplifiercircuit 5404 all at once. The amplitude of the video signal voltageV_(data) is amplified by the amplifier circuit 5404, and the videosignals are input from each signal line to the pixel portion 5201.

The video signal held in the second latch circuit 5403 is input to theamplifier circuit 5404, and while the video signal is input to the pixelportion 5201, the shift register 5401 outputs a sampling pulse again. Inother words, two operations are performed at the same time. Thus, linesequential driving can be realized. Thereafter, the above operations isrepeated.

Note that a signal is supplied to a pixel by dot sequential driving insome cases. FIG. 54B shows an example of the signal line driver circuit5204 in this case. The signal line driver circuit 5204 in this caseincludes the shift register 5401, a sampling circuit 5405, and the like.Sampling pulses are output from the shift register 5401 to the samplingcircuit 5405. A voltage V_(data) as a video signal is input to thesampling circuit 5405 from a video signal line, and the video signalsare sequentially output to the pixel portion 5201 in accordance with thesampling pulses. Thus, dot sequential driving can be realized.

Note that the signal line driver circuit or a part thereof (such as thecurrent source circuit or the amplifier circuit) is not provided overthe same substrate as the pixel portion 5201 in some cases, and may beformed using, for example, an external IC chip.

By using the scan line driver circuit and the signal line driver circuitas described above, the driving in the case where a period for writing asignal to a pixel and a lighting period are separated can be realized.

Note that a plurality of scan line driver circuits is provided in thedisplay device shown in FIG. 52; however, a plurality of signal linedriver circuits may be provided depending on a pixel configuration. Forexample, FIG. 55 shows a structure example of a display device in a casewhere the pixel configuration shown in FIG. 39 is used.

The display device shown in FIG. 55 includes a pixel portion 5501, ascan line driver circuit 5502, and first and second signal line drivercircuits 5503 and 5504. The scan line driver circuit 5502 is connectedto the scan line 3917. The first signal line driver circuit 5503 and thefirst signal line 3915 are connected. The second signal line drivercircuit 5504 and the second signal line 3925 are connected. Note thatreference numerals which denote the first and second signal lines andthe scan line correspond to the reference numerals used in FIG. 39. Inaddition, structures of the first and second signal line driver circuits5503 and 5504 and the scan line driver circuit 5502 are similar to thosedescribed in FIGS. 53 and 54; therefore, description thereof is omitted.

The scan line driver circuit 5502 sequentially outputs selection signalsto the first scan line 3917 connected to SP1 and SP2. Thus, theselection signals are written to SP1 and SP2.

The first signal line driver circuit 5503 sequentially outputs videosignals to the first signal line 3915 connected to SP1. The videosignals output from the first signal line driver circuit 5503 are inputto SP1. Further, the second signal line driver circuit 5504 sequentiallyoutputs video signals to the second signal line 3925 connected to SP2.The video signals output from the second signal line driver circuit 5504are input to SP2. An image is displayed in the pixel portion 5501 bycontrol of a light emitting state of a pixel in accordance with thevideo signals. Note that, in general, when one pixel is divided into msubpixels (m is an integer of m≧2), m signal line driver circuits may beprovided.

By using the scan line driver circuit and the signal line driver circuitas described above, the driving in the case where a period for writing asignal to a pixel and a lighting period are separated can be realized.

Next, a case is described in which an operation of erasing a signal of apixel is performed. Here, for a pixel configuration, a case of using thepixel configuration shown in FIG. 45 is described as an example. FIG. 56shows a structure example of a display device in this case.

The display device shown in FIG. 56 includes a pixel portion 5601, firstto fourth scan line driver circuits 5602 to 5605, and a signal linedriver circuit 5606. The first scan line driver circuit 5602 and thefirst scan line 4517 are connected. The second scan line driver circuit5603 and the second scan line 4527 are connected. The third scan linedriver circuit 5604 and the third scan line 4537 are connected. Thefourth scan line driver circuit 5605 and the fourth scan line 4547 areconnected. The signal line driver circuit 5606 and the signal line 4515are connected. Note that reference numerals which denote the first tofourth scan lines and the signal line correspond to the referencenumerals used in FIG. 45. In addition, structures of the first to fourthscan line driver circuits 5602 to 5605 and the signal line drivercircuit 5606 are similar to those described in FIGS. 53 and 54;therefore, description thereof is omitted.

The first and second scan line driver circuits 5602 and 5603 drive thefirst and second scan lines 4517 and 4527 connected to SP1. The firstscan line driver circuit 5602 sequentially outputs selection signals tothe first scan line 4517 connected to SP1. The second scan line drivercircuit 5603 sequentially outputs erase signals to the second scan line4527 connected to SP1. Thus, the selection signals and the erase signalsare written to SP1.

Similarly, the third and fourth scan line driver circuits 5604 and 5605drive the third and fourth scan lines 4537 and 4547 connected to SP2.The third scan line driver circuit 5604 sequentially outputs selectionsignals to the third scan line 4537 connected to SP2. The fourth scanline driver circuit 5605 sequentially outputs erase signals to thefourth scan line 4547 connected to SP2. Thus, the selection signals andthe erase signals are written to SP2.

The scan line driver circuit 5606 sequentially outputs video signals tothe signal line 4515 connected to SP1 and SP2. The video signals outputfrom the signal line driver circuit 5606 are input to the pixel portion5601.

By using the scan line driver circuits and the signal line drivercircuit described above, the driving in the case where the operation oferasing a signal of a pixel is performed can be realized.

Note that structures of a display device, a signal line driver circuit,a scan line driver circuit, and the like are not limited to those shownin FIGS. 52 to 56.

Note that a transistor in the invention can be any type of transistorsand formed over any substrate. Therefore, all the circuits shown inFIGS. 52 to 56 may be formed over a glass substrate or a plasticsubstrate, using a single crystalline substrate or an SOI substrate, orthe like. Alternatively, a part of the circuits in FIGS. 52 to 56 may beformed over one substrate, and the other part of the circuits in FIGS.52 to 56 may be formed over another substrate. In other words, it is notnecessary that all the circuits in FIGS. 52 to 56 are formed over thesame substrate. For example, in FIGS. 52 to 56, the pixel portion andthe scan line driver circuit may be formed over a glass substrate byusing transistors, and the signal line driver circuit (or a partthereof) may be formed using a single crystalline substrate, and then anIC chip may be connected by COG (Chip On Glass) to be provided over aglass substrate. Alternatively, the IC chip may be connected to theglass substrate by TAB (Tape Auto Bonding) or using a printed wiringboard. In this manner, when a part of the circuits is formed over thesame substrate, the number of components can be reduced to reduce cost,and the number of connections to circuit components can be reduced toimprove reliability. In addition, when a portion with a high drivingvoltage or a portion with high driving frequency which consumes largepower is formed over another substrate, power consumption can besuppressed.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 5.

Embodiment Mode 7

In this embodiment mode, a display panel used for a display device ofthe invention is described with reference to FIGS. 57A and 57B and thelike. FIG. 57A is a top view showing a display panel. FIG. 57B is across-sectional view along a line A-A′ of FIG. 57A. A signal line drivercircuit 5701, a pixel portion 5702, a first scan line driver circuit5703, and a second scan line driver circuit 5706, which are indicated bydotted lines, are included. A sealing substrate 5704 and a sealingmaterial 5705 are also included, and a space surrounded by the sealingmaterial 5705 is a space 5707.

A wiring 5708 transmits signals input to the first scan line drivercircuit 5703, the second scan line driver circuit 5706, and the signalline driver circuit 5701, and receives video signals, clock signals,start signals, and the like from an FPC 5709 to be an external inputterminal. An IC chip (a semiconductor chip in which a memory circuit, abuffer circuit, and the like are formed) 5719 is mounted over a junctionof the FPC 5709 and the display panel by COG (Chip On Glass) or thelike. Note that only the FPC is shown in the figure; however, a printedwiring board (PWB) may be attached to the FPC.

Next, a cross-sectional structure is described with reference to FIG.57B. The pixel portion 5702 and peripheral driver circuits (the firstscanning line driver circuit 5703, the second scanning line drivercircuit 5706, and the signal line driver circuit 5701) are formed over asubstrate 5710. Here, the signal line driver circuit 5701 and the pixelportion 5702 are shown.

Note that the signal line driver circuit 5701 is formed using aplurality of transistors such as a transistor 5720 and a transistor5721. In this embodiment mode, a display panel in which the peripheraldriver circuits are formed over the same substrate is described;however, it is not always necessary, and all or a part of the peripheraldriver circuits may be formed in an IC chip or the like and mounted byCOG or the like.

In addition, the pixel portion 5702 includes a plurality of circuitsforming a pixel including a selection transistor 5711 and a drivingtransistor 5712. Note that a source electrode of the driving transistor5712 is connected to a first electrode 5713. An insulator 5714 is formedto cover an end portion of the first electrode 5713. Here, a positivephotosensitive acrylic resin film is used.

In addition, for good coverage, a curved surface having curvature isformed at an upper end portion or a lower end portion of the insulator5714. For example, when positive photosensitive acrylic is used as amaterial for the insulator 5714, a curved surface having a curvatureradius (0.2 to 3 μm) is preferably provided only at the upper endportion of the insulator 5714. Further, as the insulator 5714, eithernegative photosensitive acrylic to be insoluble in etchant by lightirradiation or positive photosensitive acrylic to be soluble in etchantby light irradiation can be used.

A layer 5716 containing an organic compound and a second electrode 5717are formed over the first electrode 5713. Here, as a material used forthe first electrode 5713 functioning as an anode, a material with a highwork function is preferably used. For example, a single layer film suchas an ITO (indium tin oxide) film, an indium zinc oxide (IZO) film, atitanium nitride film, a chromium film, a tungsten film, a Zn film, or aPt film; a stacked-layer structure of a titanium nitride film and a filmcontaining aluminum as its main component; a three-layer structure of atitanium nitride film, a film containing aluminum as its main component,and a titanium nitride film, and the like can be used. Note that in acase of a stacked-layer structure, resistance for a wiring is low, goodohmic contact is obtained, and a function as an anode can be obtained.

The layer 5716 containing the organic compound is formed by a vapordeposition method using a vapor deposition mask or by an ink-jet method.A metal complex using a metal from group 4 of the periodic table is usedfor a part of the layer 5716 containing the organic compound, and a lowmolecular weight material or a high molecular weight material may beused in combination. Further, for a material used for the layercontaining the organic compound, a single layer or a stacked layer of anorganic compound is often used; however, in this embodiment, aninorganic compound may be used in a part of a film formed of an organiccompound. Moreover, a known triplet material can also be used.

Further, as a material used for the second electrode 5717, which is acathode, formed over the layer 5716 containing the organic compound, amaterial with a low work function (Al, Ag, Li, Ca, or an alloy thereofsuch as MgAg, MgIn, AlLi, CaF₂, or calcium nitride) may be used. Notethat when light generated in the layer 5716 containing the organiccompound is transmitted through the second electrode 5717, astacked-layer structure of a metal thin film and a transparentconductive film (ITO (indium tin oxide), an indium oxide-zinc oxidealloy (In₂O₃—ZnO), zinc oxide (ZnO), or the like) is preferably used asthe second electrode 5717.

In addition, the sealing substrate 5704 is attached to the substrate5710 by the sealing material 5705 to have a structure provided with alight emitting element 5718 in the space 5707 surrounded by thesubstrate 5710, the sealing substrate 5704, and the sealing material5705. Note that the space 5707 may be filled with the sealing material5705 or with an inert gas (such as nitrogen or argon).

Note that an epoxy-based resin is preferably used for the sealingmaterial 5705. Further, it is preferable that these materials transmitas little moisture or oxygen as possible. In addition, as a materialused for the sealing substrate 5704, a plastic substrate formed usingFRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar (aregistered trademark), polyester, acrylic, or the like as well as aglass substrate or a quartz substrate can be used.

As described above, a display panel having a pixel configuration of theinvention can be obtained.

As shown in FIGS. 57A and 57B, the signal line driver circuit 5701, thepixel portion 5702, the first scan line driver circuit 5703, and thesecond scan line driver circuit 5706 are formed over the same substrate,and thereby, reduction in cost of the display device can be realized.Further, when unipolar transistors are used for the signal line drivercircuit 5701, the pixel portion 5702, the first scan line driver circuit5703, and the second scan line driver circuit 5706, simplification of amanufacturing process can be realized, and thereby, further costreduction can be realized. When amorphous silicon is employed assemiconductor layers of transistors used for the signal line drivercircuit 5701, the pixel portion 5702, the first scan line driver circuit5703, and the second scan line driver circuit 5706, further costreduction can be realized.

Note that the structure of the display panel is not limited to thestructure shown in FIG. 57A, in which the signal line driver circuit5701, the pixel portion 5702, the first scan line driver circuit 5703,and the second scan line driver circuit 5706 are formed over the samesubstrate, and a signal line driver circuit corresponding to the signalline driver circuit 5701 may be formed over an IC chip and mounted onthe display panel by COG or the like.

That is, only the signal line driver circuit of which high speedoperation is required is formed into an IC chip using a CMOS or thelike, and thereby, lower power consumption is realized. Further, when asemiconductor chip formed of a silicon wafer or the like is used as theIC chip, higher speed operation and lower power consumption can beachieved.

Cost reduction can be realized by forming the scan line driver circuitsand the pixel portion over the same substrate. Note that when unipolartransistors are used for the scan line driver circuits and the pixelportion, further cost reduction can be realized. As a structure of apixel included in the pixel portion, the structures shown in EmbodimentMode 4 can be employed. When amorphous silicon is used for semiconductorlayers of transistors, the manufacturing process can be simplified, andfurther cost reduction can be realized.

As described above, cost reduction of a high-definition display devicecan be realized. Further, by mounting an IC chip including a functionalcircuit (memory or buffer) over the junction of the FPC 5709 and thesubstrate 5710, a substrate area can be effectively utilized.

Further, a signal line driver circuit, first and second scan line drivercircuits which correspond to the signal line driver circuit 5701, andthe first scan line driver circuit 5703, and the second scan line drivercircuit 5706 in FIG. 57A may be formed over an IC chip and mounted on adisplay panel by COG or the like. In this case, reduction in powerconsumption of a high-definition display device can be realized.Accordingly, in order to obtain a display device with less powerconsumption, polysilicon is preferably used for semiconductor layers oftransistors used in the pixel portion.

In addition, when amorphous silicon is used for semiconductor layers oftransistors in the pixel portion 5702, further cost reduction can berealized. Moreover, a large display panel can be manufactured as well.

Note that the signal line driver circuit and the scan line drivercircuit are not limited to being provided in a row direction and acolumn direction of the pixels.

Next, FIG. 58 shows an example of a light emitting element which can beapplied to the light emitting element 5718.

An element structure is such that an anode 5802, a hole injecting layer5803 formed of a hole injecting material, a hole transporting layer 5804formed of a hole transporting material, a light emitting layer 5805, anelectron transporting layer 5806 formed of an electron transportingmaterial, an electron injecting layer 5807 formed of an electroninjecting material, and a cathode 5808 are stacked over a substrate5801. Here, the light emitting layer 5805 is formed of only one kind ofa light emitting material in some cases and formed of two or more kindsof materials in other cases. A structure of the element of the inventionis not limited thereto.

In addition to the stacked-layer structure shown in FIG. 58, in whichfunctional layers are stacked, there are wide variations such as anelement formed using a high molecular compound and a high efficiencyelement utilizing a triplet light emitting material which emits lightfrom a triplet excitation state in a light emitting layer. Thesevariations can also be applied to a white light emitting element whichcan be obtained by dividing a light emitting region into two regions bycontrol of a recombination region of carriers using a hole blockinglayer and the like.

Next, a manufacturing method of the element of the invention shown inFIG. 58 is described. First, a hole injecting material, a holetransporting material, and a light emitting material are sequentiallydeposited over the substrate 5801 including the anode 5802 (ITO (indiumtin oxide)). Next, an electron transporting material and an electroninjecting material are deposited, and finally, the cathode 5808 isformed by evaporation.

Next, materials suitable for the hole injecting material, the holetransporting material, the electron transporting material, the electroninjecting material, and the light emitting material are described asfollows.

As the hole injecting material, an organic compound such as aporphyrin-based compound, phthalocyanine (hereinafter referred to asH₂Pc), copper phthalocyanine (hereinafter referred to as CuPc), or thelike is effective. A material which has a lower ionization potentialthan that of the hole transporting material to be used and has a holetransporting function can also be used as the hole injecting material.Further, a material, such as polyaniline and polyethylene dioxythiophene(hereinafter referred to as PEDOT) doped with polystyrene sulfonate(hereinafter referred to as PSS), obtained by chemically doping aconductive high molecular compound may also employed. Further, aninsulating high molecular compound is effective in planarization of theanode, and polyimide (hereinafter referred to as PI) is often used.Further, an inorganic compound which includes an ultrathin film ofaluminum oxide (hereinafter referred to as “alumina”) as well as a thinfilm of a metal such as gold or platinum is also used.

As the hole transporting material, an aromatic amine-based compound(that is, a compound having a benzene ring-nitrogen bond) is most widelyused. A material which is widely used as the hole transporting materialincludes 4,4′-bis(diphenylamino)-biphenyl (hereinafter referred to asTAD), derivatives thereof such as4,4′-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (hereinafterreferred to as TPD), and4,4′-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (hereinafter referredto as α-NPD), and starburst aromatic amine compounds such as4,4′,4″-tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred toas TDATA) and4,4′,4″-tris[N-(3-methylphenyl)-N-phenyl-amino]-triphenylamine(hereinafter referred to as MTDATA).

As the electron transporting material, a metal complex is often used,which includes a metal complex having a quinoline skeleton or abenzoquinoline skeleton, such as tris(8-quinolinolato)aluminum(hereinafter referred to as Alq₃), BAlq,tris(4-methyl-8-quinolinolato)aluminum (hereinafter referred to asAlmq), or bis(10-hydroxybenzo[h]-quinolinato)beryllium (hereinafterreferred to as Bebq). In addition, a metal complex having anoxazole-based or a thiazole-based ligand such asbis[2-(2-hydroxyphenyl)-benzoxazolato]zinc (hereinafter referred to asZn(BOX)₂) or bis[2-(2-hydroxyphenyl)-benzothiazolato]zinc (hereinafterreferred to as Zn(BTZ)₂) may be employed. Further, in addition to themetal complexes, oxadiazole derivatives such as2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (hereinafterreferred to as PBD) and OXD-7, triazole derivatives such as TAZ and3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole(hereinafter referred to as p-EtTAZ), and phenanthroline derivativessuch as bathophenanthroline (hereinafter referred to as BPhen) and BCPhave electron transporting properties

As the electron injecting material, the above-mentioned electrontransporting materials can be used. In addition, an ultrathin film of aninsulator, for example, metal halide such as calcium fluoride, lithiumfluoride, or cesium fluoride or alkali metal oxide such as lithium oxideis often used. Further, an alkali metal complex such as lithium acetylacetonate (hereinafter referred to as Li(acac)) or8-quinolinolato-lithium (hereinafter referred to as Liq) is alsoeffective.

As the light emitting material, in addition to the above-mentioned metalcomplexes such as Alg₃, Almq, BeBq, BAlq, Zn(BOX)₂, and Zn(BTZ)₂,various fluorescent pigments are effective. The fluorescent pigmentsinclude 4,4′-bis(2,2-diphenyl-vinyl)-biphenyl, which is blue, and4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran, whichis red-orange, and the like. In addition, a triplet light emittingmaterial which mainly includes a complex with platinum or iridium as acentral metal is available. As the triplet light emitting material,tris(2-phenylpyridine)iridium,bis(2-(4′-tolyl)pyridinato-N,C^(2′))acetylacetonato iridium (hereinafterreferred to as acacIr(tpy)₂),2,3,7,8,12,13,17,18-octaethyl-21H,23Hporphyrin-platinum, and the likeare known.

By using the materials having each function as described above incombination, a highly reliable light emitting element can be formed.

A light emitting element of which layers are formed in reverse order ofthat in FIG. 58 can also be used. That is, the cathode 5808, theelectron injecting layer 5807 formed of the electron injecting material,the electron transporting layer 5806 formed of the electron transportingmaterial, the light emitting layer 5805, the hole transporting layer5804 formed of the hole transporting material, the hole injecting layer5803 formed of the hole injecting material, and the anode 5802 aresequentially stacked over the substrate 5801.

In addition, at least one of the anode and the cathode of the lightemitting element is necessary to be transparent in order to extractlight emission. A transistor and a light emitting element are formedover a substrate; and there are light emitting elements having a topemission structure where light emission is extracted from a surface onthe side opposite to the substrate, having a bottom emission structurewhere light emission is extracted from a surface on the substrate side,and having a dual emission structure where light emission is extractedfrom both the surface on the side opposite to the substrate and thesurface on the substrate side. A pixel configuration of the inventioncan be applied to a light emitting element having any emissionstructure.

A light emitting element having a top emission structure is describedwith reference to FIG. 59A.

A driving transistor 5901 is formed over a substrate 5900. A firstelectrode 5902 is formed in contact with a source electrode of thedriving TFT 5901, and a layer 5903 containing an organic compound and asecond electrode 5904 are formed thereover.

The first electrode 5902 is an anode of the light emitting element. Thesecond electrode 5904 is a cathode of the light emitting element. Thatis, a region where the layer 5903 containing the organic compound isinterposed between the first electrode 5902 and the second electrode5904 functions as the light emitting element.

As a material used for the first electrode 5902 which functions as theanode, a material having a high work function is preferably used. Forexample, a single layer of a titanium nitride film, a chromium film, atungsten film, a Zn film, a Pt film, or the like, a stacked-layerstructure of a titanium nitride film and a film containing aluminum asits main component, a three-layer structure of a titanium nitride film,a film containing aluminum as its main component, and a titanium nitridefilm, or the like can be used. Note that in a case of a stacked-layerstructure, the resistance as a wiring is low, a good ohmic contact canbe obtained, and further, a function as an anode can be achieved. Byusing a metal film which reflects light, an anode which does nottransmit light can be formed.

As a material used for the second electrode 5904 which functions as thecathode, a stacked layer of a thin metal film formed of a materialhaving a low work function (Al, Ag, Li, Ca, or an alloy thereof such asMgAg, MgIn, AlLi, CaF₂, or calcium nitride) and a transparent conductivefilm (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO),or the like) is preferably used. By using a thin metal film and atransparent conductive film having light transmitting properties, acathode which can transmit light can be formed.

As described above, light from the light emitting element can beextracted from a top surface as shown by an arrow in FIG. 59A. That is,when the display panel shown in FIGS. 57A and 57B is employed, light isemitted toward the sealing substrate 5704 side. Therefore, when a lightemitting element having a top emission structure is employed in adisplay device, a substrate having light transmitting properties is usedas the sealing substrate 5704.

When an optical film is provided, the sealing substrate 5704 is providedwith an optical film.

Note that a metal film formed of a material such as MgAg, MgIn, or AlLi,which functions as a cathode and has a low work function can be used forthe first electrode 5902. In this case, a transparent conductive film,such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO)film, can be used for the second electrode 5904. Therefore, thetransmittance of the top light emission can be improved with thisstructure.

Next, a light emitting element having a bottom emission structure isdescribed with reference to FIG. 59B. The same reference numerals asthose in FIG. 59A are used since the structure of the light emittingelement is the same except for the light emission structure.

Here, as a material used for the first electrode 5902 which functions asthe anode, a material having a high work function is preferably used.For example, a transparent conductive film such as an ITO (indium tinoxide) film or an indium zinc oxide (IZO) film can be used. By using atransparent conductive film having light transmitting properties, ananode which can transmit light can be formed.

As a material used for the second electrode 5904 which functions as thecathode, a metal film formed of a material having a low work function(Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF₂, orcalcium nitride) can be used. By using a metal film which reflectslight, a cathode which does not transmit light can be formed.

As described above, light from the light emitting element can beextracted from a bottom surface as shown by an arrow in FIG. 59B. Thatis, when the display panel shown in FIGS. 57A and 57B is employed, lightis emitted toward the substrate 5710 side. Therefore, when a lightemitting element having a bottom emission structure is employed in adisplay device, a substrate having light transmitting properties is usedas the substrate 5710.

When an optical film is provided, the substrate 5710 is provided with anoptical film.

Next, a light emitting element having a dual emission structure isdescribed with reference to FIG. 59C. The same reference numerals asthose in FIG. 59A are used since the structure of the light emittingelement is the same except for the light emission structure.

Here, as a material used for the first electrode 5902 which functions asthe anode, a material having a high work function is preferably used.For example, a transparent conductive film such as an ITO (indium tinoxide) film or an indium zinc oxide (IZO) film can be used. By using atransparent conductive film having light transmitting properties, ananode which can transmit light can be formed.

As a material used for the second electrode 5904 which functions as thecathode, a stacked layer of a thin metal film formed of a materialhaving a low work function (Al, Ag, Li, Ca, or an alloy thereof such asMgAg, Men, AlLi, CaF₂, or calcium nitride) and a transparent conductivefilm (ITO (indium tin oxide), indium oxide zinc-oxide alloy (In₂O₃—ZnO),zinc oxide (ZnO), or the like) can be used. By using a thin metal filmand a transparent conductive film having light transmitting properties,a cathode which can transmit light can be formed.

As described above, light from the light emitting element can beextracted from both sides as shown by arrows in FIG. 59C. That is, whenthe display panel shown in FIGS. 57A and 57B is employed, light isemitted toward the substrate 5710 side and the sealing substrate 5704side. Therefore, when a light emitting element having a dual emissionstructure is employed in a display device, substrate having lighttransmitting properties are used for both the substrate 5710 and thesealing substrate 5704.

When an optical film is provided, both the substrate 5710 and thesealing substrate 5704 is provided with an optical film.

In addition, the invention can be applied to a display device in whichfull color display is realizing by using a white light emitting elementand a color filter.

As shown in FIG. 60, a base film 6002 is formed over a substrate 6000,and a driving transistor 6001 is formed over the base film 6002. A firstelectrode 6003 is formed in contact with a source electrode of thedriving transistor 6001, and a layer 6004 containing an organic compoundand a second electrode 6005 are formed thereover.

The first electrode 6003 is an anode of a light emitting element. Thesecond electrode 6005 is a cathode of the light emitting element. Thatis, a region where the layer 6004 containing the organic compound isinterposed between the first electrode 6003 and the second electrode6005 functions as the light emitting element. In the structure shown inFIG. 60, white light is emitted. A red color filter 6006R, a green colorfilter 6006G, and a blue color filter 6006B are provided over the lightemitting elements; thus, full color display can be performed. Further, ablack matrix (also referred to as a BM) 6007 which separates these colorfilters is provided.

The aforementioned structures of the light emitting element can be usedin combination and can be applied to the display device of the inventionas appropriate. The structures of the display panel and the lightemitting elements which are described above are only examples, and theinvention can be applied to a display device having another structure.

Next, a partial cross-sectional view of a pixel portion of a displaypanel is shown.

First, a case where a polysilicon (p-Si) film is used as a semiconductorlayer of a transistor is described with reference to FIGS. 61A to 63B.

Here, the semiconductor layer is obtained by forming an amorphoussilicon (a-Si) film over a substrate by a known film formation method,for example. Note that it is not limited to the amorphous silicon film,and any semiconductor film having an amorphous structure (including amicrocrystalline semiconductor film) may be used. Further, a compoundsemiconductor film having an amorphous structure, such as an amorphoussilicon germanium film, may be used.

Then, the amorphous silicon film is crystallized by a lasercrystallization method, a thermal crystallization method using RTA or anannealing furnace, a thermal crystallization method using a metalelement which promotes crystallization, or the like. It is needless tosay that such crystallization methods may be performed in combination.

As a result of the aforementioned crystallization, a crystallized regionis formed in a part of the amorphous semiconductor film.

Further, the crystalline semiconductor film in which part is made morecrystallized is patterned into a desired shape, and an island-shapedsemiconductor film is formed using the crystallized region. Thissemiconductor film is used as the semiconductor layer of the transistor.

As shown in FIG. 61A, a base film 6102 is formed over a substrate 6101,and a semiconductor layer is formed thereover. The semiconductor layerincludes a channel forming region 6103, an LDD region 6104, and animpurity region 6105 to be a source region or drain region of a drivingtransistor 6118; and a channel forming region 6106, an LDD region 6107,and an impurity region 6108 to be a lower electrode of a capacitor 6119.Note that channel doping may be performed on the channel forming region6103 and the channel forming region 6106.

As the substrate, a glass substrate, a quartz substrate, a ceramicsubstrate, or the like can be used. As the base film 6102, a singlelayer of aluminum nitride (AlN), silicon oxide (SiO₂), siliconoxynitride (SiOxNy), or the like, or stacked layers thereof can be used.

A gate electrode 6110 and an upper electrode 6111 of the capacitor 6119are formed over the semiconductor layer with a gate insulating film 6109interposed therebetween.

An interlayer insulating film 6112 is formed to cover the capacitor 6119and the driving transistor 6118. A wiring 6113 is in contact with theimpurity region 6105 over the interlayer insulating film 6112 through acontact hole. A pixel electrode 6114 is formed in contact with thewiring 6113. An insulator 6115 is formed to cover end portions of thepixel electrode 6114 and the wiring 6113. Here, the insulator 6115 isformed using a positive photosensitive acrylic resin film. Then, a layer6116 containing an organic compound and an opposite electrode 6117 areformed over the pixel electrode 6114. A light emitting element 6120 isformed in a region where the layer 6116 containing the organic compoundis interposed between the pixel electrode 6114 and the oppositeelectrode 6117.

Alternatively, as shown in FIG. 61B, a region 6121 may be provided sothat the LDD region which forms a part of the lower electrode of thecapacitor 6119 overlaps with the upper electrode 6111 of the capacitor6119. Note that portions in common with those in FIG. 61A are denoted bythe same reference numerals, and description thereof is omitted.

Alternatively, as shown in FIG. 62A, a capacitor 6123 may include asecond upper electrode 6122 which is formed in the same layer as thewiring 6113 in contact with the impurity region 6105 of the drivingtransistor 6118. Note that portions in common with those in FIG. 61A aredenoted by the same reference numerals, and description thereof isomitted. Since the second upper electrode 6122 is in contact with theimpurity region 6108, a first capacitor having a structure where thegate insulating film 6109 is interposed between the upper electrode 6111and the channel forming region 6106, and a second capacitor having astructure where the interlayer insulating film 6112 is interposedbetween the upper electrode 6111 and the second upper electrode 6122 areconnected in parallel, so that the capacitor 6123 including the firstcapacitor and the second capacitor is formed. Since the capacitor 6123has the total capacitance of the first capacitor and the secondcapacitor, a capacitor having a large capacitance can be formed in asmall area. That is, an aperture ratio can be improved by using thecapacitor having the pixel configuration of the invention.

Alternatively, a capacitor may have a structure shown in FIG. 62B. Abase film 6202 is formed over a substrate 6201, and a semiconductorlayer is formed thereover. The semiconductor layer includes a channelforming region 6203, an LDD region 6204, and an impurity region 6205 tobe a source region or drain region of a driving transistor 6218. Notethat channel doping may be performed on the channel forming region 6203.

As the substrate, a glass substrate, a quartz substrate, a ceramicsubstrate, or the like can be used. As the base film 6202, a singlelayer of aluminum nitride (AlN), silicon oxide (SiO₂), siliconoxynitride (SiOxNy), or the like, or stacked layers thereof can be used.

A gate electrode 6207 and a first electrode 6208 are formed over thesemiconductor layer with a gate insulating film 6206 interposedtherebetween.

A first interlayer insulating film 6209 is formed to cover the drivingtransistor 6218 and the first electrode 6208. A wiring 6210 is incontact with the impurity region 6205 over the first interlayerinsulating film 6209 through a contact hole. A second electrode 6211 isformed in the same layer and of the same material as the wiring 6210.

Further, a second interlayer insulating film 6212 is formed to cover thewiring 6210 and the second electrode 6211. A pixel electrode 6213 isformed in contact with the wiring 6210 over the second interlayerinsulating film 6212 through a contact hole. A third electrode 6214 isformed in the same layer and of the same material as the pixel electrode6213. An insulator 6215 is formed to cover end portions of the pixelelectrode 6213 and the third electrode 6214. The insulator 6215 isformed using, for example, a positive photosensitive acrylic resin film.Here, a capacitor 6219 is formed of the first electrode 6208, the secondelectrode 6211, and the third electrode 6214.

A layer 6216 containing an organic compound and an opposite electrode6217 are formed over the pixel electrode 6213. A light emitting element6220 is formed in a region where the layer 6216 containing the organiccompound is interposed between the pixel electrode 6213 and the oppositeelectrode 6217.

As described above, the structures shown in FIGS. 61A to 62B can begiven as examples of a structure of a transistor in which a crystallinesemiconductor film is used for its semiconductor layer. Note that thestructures of the transistor shown in FIGS. 61A to 62B are examples of atop gate transistor. That is, the LDD region may overlap with the gateelectrode or not, or a part of the LDD region may overlap with the gateelectrode. Further, the gate electrode may have a tapered shape, and theLDD region may be provided below the tapered portion of the gateelectrode in a self-aligned manner. In addition, the number of gateelectrodes is not limited to two, and a multi-gate structure with threeor more gate electrodes may be employed, or a single gate structure mayalso be employed.

When a crystalline semiconductor film is used for a semiconductor layer(a channel forming region, a source region, a drain region, and thelike) of a transistor included in the pixel of the invention, the scanline driver circuit and the signal line driver circuit are easily formedover the same substrate as the pixel portion. Further, a part of thescan line driver circuit may be formed over the same substrate as thepixel portion, and the other part of the scan line driver circuit may beformed over an IC chip and mounted by COG or the like as shown in FIGS.57A and 57B. By such a structure, reduction in manufacturing cost can berealized.

As a structure of a transistor which uses polysilicon (p-Si:H) for itssemiconductor layer, a structure where a gate electrode is interposedbetween a substrate and a semiconductor layer, in other words, a bottomgate structure where a gate electrode is located below a semiconductorlayer may be applied. FIGS. 63A and 63B each show a partialcross-sectional view of a pixel portion of a display panel in which abottom gate transistor is employed.

As shown in FIG. 63A, a base film 6302 is formed over a substrate 6301.A gate electrode 6303 is formed over the base film 6302. A firstelectrode 6304 is formed in the same layer and of the same material asthe gate electrode 6303. As a material for the gate electrode 6303,polycrystalline silicon to which phosphorus is added can be used. Inaddition to polycrystalline silicon, silicide, which is a compound of ametal and silicon, may be employed.

A gate insulating film 6305 is formed to cover the gate electrode 6303and the first electrode 6304. As the gate insulating film 6305, asilicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer is formed over the gate insulating film 6305. Thesemiconductor layer includes a channel forming region 6306, an LDDregion 6307, and an impurity region 6308 to be a source region or drainregion of a driving transistor 6322, and a channel forming region 6309,an LDD region 6310, and an impurity region 6311 to be a second electrodeof a capacitor 6323. Note that channel doping may be performed on thechannel forming region 6306 and the channel forming region 6309.

As the substrate, a glass substrate, a quartz substrate, a ceramicsubstrate, or the like can be used. As the base film 6302, a singlelayer of aluminum nitride (AlN), silicon oxide (SiO₂), siliconoxynitride (SiOxNy), or the like, or stacked layers thereof can be used.

A first interlayer insulating film 6312 is formed to cover thesemiconductor layer. A wiring 6313 is in contact with the impurityregion 6308 over the first interlayer insulating film 6312 through acontact hole. A third electrode 6314 is formed in the same layer and ofthe same material as the wiring 6313. The capacitor 6323 is formed ofthe first electrode 6304, the second electrode, and the third electrode6314.

In addition, an opening 6315 is formed in the first interlayerinsulating film 6312. A second interlayer insulating film 6316 is formedto cover the driving transistor 6322, the capacitor 6323, and theopening 6315. A pixel electrode 6317 is formed over the secondinterlayer insulating film 6316 through a contact hole. Then, aninsulator 6318 is formed to cover end portions of the pixel electrode6317. As the insulator, a positive photosensitive acrylic resin film canbe used, for example. A layer 6319 containing an organic compound and anopposite electrode 6320 are formed over the pixel electrode 6317. Alight emitting element 6321 is formed in a region where the layer 6319containing the organic compound is interposed between the pixelelectrode 6317 and the opposite electrode 6320. The opening 6315 islocated below the light emitting element 6321. That is, when lightemitted from the light emitting element 6321 is extracted from thesubstrate side, the transmittance can be improved since the opening 6315is provided.

Alternatively, a structure shown in FIG. 63B, in which a fourthelectrode 6324 is formed in the same layer and of the same material asthe pixel electrode 6317 in FIG. 63A, may be employed. Thus, a capacitor6325 can be formed of the first electrode 6304, the second electrode,the third electrode 6314, and the fourth electrode 6324.

Next, the case where an amorphous silicon (a-Si:H) film is used for asemiconductor layer of a transistor is described with reference to FIGS.64A to 66B.

FIGS. 64A and 64B show partial cross-sectional views of a transistorhaving a top gate structure, which uses amorphous silicon for itssemiconductor layer. As shown in FIG. 64A, a base film 6402 is formedover a substrate 6401. A pixel electrode 6403 is formed over the basefilm 6402. A first electrode 6404 is formed in the same layer and of thesame material as the pixel electrode 6403.

As the substrate, a glass substrate, a quartz substrate, a ceramicsubstrate, or the like can be used. As the base film 6402, a singlelayer of aluminum nitride (AlN), silicon oxide (SiO₂), siliconoxynitride (SiOxNy), or the like, or stacked layers thereof can be used.

A wiring 6405 and a wiring 6406 are formed over the base film 6402, andan end portion of the pixel electrode 6403 is covered with the wiring6405. An n-type semiconductor layer 6407 and an n-type semiconductorlayer 6408 each having n-type conductivity are formed over the wiring6405 and the wiring 6406, respectively. In addition, a semiconductorlayer 6409 is formed between the wiring 6405 and the wiring 6406 andover the base film 6402. A part of the semiconductor layer 6409 extendsover the n-type semiconductor layers 6407 and 6408. Note that thissemiconductor layer is formed of a semiconductor film havingnon-crystallinity, such as of amorphous silicon (a-Si:H) or amicrocrystalline semiconductor (μc-Si:H).

A gate insulating film 6410 is formed over the semiconductor layer 6409.An insulating film 6411 formed in the same layer and of the samematerial as the gate insulating film 6410 is also formed over the firstelectrode 6404. Note that as the gate insulating film 6410, a siliconoxide film, a silicon nitride film, or the like is used.

A gate electrode 6412 is formed over the gate insulating film 6410. Asecond electrode 6413 which is formed in the same layer and of the samematerial as the gate electrode 6412 is formed over the first electrode6404 with the insulating film 6411 interposed therebetween. Thus, acapacitor 6419 in which the insulating film 6411 is interposed betweenthe first electrode 6404 and the second electrode 6413 is formed. Aninterlayer insulating film 6414 is formed to cover an end portion of thepixel electrode 6403, a driving transistor 6418, and the capacitor 6419.

A layer 6415 containing an organic compound and an opposite electrode6416 are formed over the interlayer insulating film 6414 and the pixelelectrode 6403 located in an opening of the interlayer insulator 6414. Alight emitting element 6417 is formed in a region where the layer 6415containing the organic compound is interposed between the pixelelectrode 6403 and the opposite electrode 6416.

As shown in FIG. 64B, a first electrode 6420 may be formed instead ofthe first electrode 6404 shown in FIG. 64A. Note that the firstelectrode 6420 is formed in the same layer and of the same material asthe wirings 6405 and 6406.

Next, FIGS. 65A to 66B show partial cross-sectional views of a displaypanel including a bottom gate transistor which uses amorphous siliconfor its semiconductor layer.

As shown in FIG. 65A, a base film 6502 is formed over a substrate 6501.A gate electrode 6503 is formed over the base film 6502. A firstelectrode 6504 is formed in the same layer and of the same material asthe gate electrode 6503. As a material for the gate electrode 6503,polycrystalline silicon to which phosphorus is added can be used. Inaddition to polycrystalline silicon, silicide, which is a compound of ametal and silicon, may be used.

A gate insulating film 6505 is formed to cover the gate electrode 6503and the first electrode 6504. As the gate insulating film 6505, asilicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer 6506 is formed over the gate insulating film 6505.Further, a semiconductor layer 6507 is formed in the same layer and ofthe same material as the semiconductor layer 6506.

As the substrate, a glass substrate, a quartz substrate, a ceramicsubstrate, or the like can be used. As the base film 6502, a singlelayer of aluminum nitride (AlN), silicon oxide (SiO₂), siliconoxynitride (SiOxNy), or the like, or stacked layers thereof can be used.

N-type semiconductor layers 6508 and 6509 each having n-typeconductivity are formed over the semiconductor layer 6506. An n-typesemiconductor layer 6510 is formed over the semiconductor layer 6507.

Wirings 6511 and 6512 are formed over the n-type semiconductor layers6508 and 6509, respectively. A conductive layer 6513, which is formed inthe same layer and of the same material as the wirings 6511 and 6512, isformed over the n-type semiconductor layer 6510.

Thus, a second electrode is formed of the semiconductor layer 6507, then-type semiconductor layer 6510, and the conductive layer 6513. Notethat a capacitor 6520 in which the gate insulating film 6505 isinterposed between the second electrode and the first electrode 6504 isformed.

One end portion of the wiring 6511 is extended, and a pixel electrode6514 is formed to be in contact with an upper portion of the extendedwiring 6511.

An insulator 6515 is formed to cover an end portion of the pixelelectrode 6514, a driving transistor 6519, and the capacitor 6520.

A layer 6516 containing an organic compound and an opposite electrode6517 are formed over the pixel electrode 6514 and the insulator 6515. Alight emitting element 6518 is formed in a region where the layer 6516containing the organic compound is interposed between the pixelelectrode 6514 and the opposite electrode 6517.

Note that the semiconductor layer 6507 and the n-type semiconductorlayer 6510 to be a part of the second electrode of the capacitor 6520are not necessary to be formed. That is, the second electrode of thecapacitor 6520 may be the conductive layer 6513 so that the capacitor6520 has a structure where the gate insulating film is interposedbetween the first electrode 6504 and the conductive layer 6513.

Note that in FIG. 65A, the pixel electrode 6514 may be formed before thewiring 6511 is formed, whereby a second electrode 6521 can be formed inthe same layer and of the same material as the pixel electrode 6514, asshown in FIG. 65B. Thus, a capacitor 6522 in which the gate insulatingfilm 6505 is interposed between the second electrode 6521 and the firstelectrode 6504 can be formed.

Note that although FIGS. 65A and 65B each show an example where aninverted staggered channel-etched transistor is applied, a channelprotective transistor may also be used. A case where a channelprotective transistor is applied is described with reference to FIGS.66A and 66B.

A channel protective transistor shown in FIG. 66A is different from thedriving transistor 6519 having a channel-etched structure shown in FIG.65A in that an insulator 6601 to be an etching mask is provided over aregion where a channel of the semiconductor layer 6506 is to be formed.Common portions are denoted by the same reference numerals.

Similarly, a channel protective transistor shown in FIG. 66B isdifferent from the driving transistor 6519 having a channel-etchedstructure shown in FIG. 65B in that an insulator 6601 to be an etchingmask is provided over the region where a channel of the semiconductorlayer 6506 is to be formed. Common portions except that point aredenoted by the same reference numerals.

When an amorphous semiconductor film is used for a semiconductor layer(a channel forming region, a source region, a drain region, and thelike) of a transistor included in the pixel of the invention,manufacturing cost can be reduced.

Note that structures of the transistor and the capacitor which can beused in the pixel portion in the display device of the invention are notlimited to those described above, and transistors and capacitors withvarious structures can be used.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 6.

Embodiment Mode 8

In this embodiment mode, a method for manufacturing a semiconductordevice by using plasma treatment is described as a method formanufacturing a semiconductor device including a transistor.

FIGS. 67A to 67C show diagrams showing a structure example of asemiconductor device including a transistor. FIG. 67B corresponds to across-sectional view along a line a-b in FIG. 67A, and FIG. 67Ccorresponds to a cross-sectional view along a line c-d in FIG. 67A.

A semiconductor device shown in FIGS. 67A to 67C includes semiconductorfilms 6703 a and 6703 b which are formed over a substrate 6701 with aninsulating film 6702 interposed therebetween, a gate electrode 6705which is formed over the semiconductor films 6703 a and 6703 b with agate insulating film 6704 interposed therebetween, insulating films 6706and 6707 which are formed to cover the gate electrode, and a conductivefilm 6708 which is connected to a source region or drain region of thesemiconductor films 6703 a and 6703 b and formed over the insulatingfilm 6707. Note that FIGS. 67A to 67C show a case where an n-channeltransistor 6710 a which uses a part of the semiconductor film 6703 a asa channel region and a p-channel transistor 6710 b which uses a part ofthe semiconductor film 6703 b as a channel region are provided; however,the structure is not limited thereto. For example, in FIGS. 67A to 67C,although an LDD region is provided in the n-channel transistor 6710 aand no LDD region is provided in the p-channel transistor 6710 b, astructure where LDD regions are provided in both transistors or astructure where an LDD region is provided in neither of the transistorscan be applied.

Note that in this embodiment mode, at least one of the substrate 6701,the insulating film 6702, the semiconductor films 6703 a and 6703 b, thegate insulating film 6704, the insulating film 6706 and the insulatingfilm 6707 is oxidized or nitrided by plasma treatment to oxidize ornitride the semiconductor film or the insulating film, so that thesemiconductor device shown in FIGS. 67A to 67C is manufactured. Byoxidizing or nitriding the semiconductor film or the insulating film byplasma treatment in such a manner, a surface of the semiconductor filmor the insulating film is modified, and the insulating film can beformed to be denser than an insulating film formed by a CVD method or asputtering method; thus, a defect such as a pinhole can be suppressed,and characteristics and the like of the semiconductor device can beimproved.

In this embodiment mode, a method is described with reference todrawings, in which a semiconductor device is manufactured by performingplasma treatment on the semiconductor films 6703 a and 6703 b or thegate insulating film 6704 in FIGS. 67A to 67C and oxidizing or nitridingthe semiconductor films 6703 a and 6703 b or the gate insulating film6704.

First, a case is shown in which an island-shaped semiconductor film ofwhich end portion is formed at an angle of about 90 degrees is providedover a substrate.

First, the island-shaped semiconductor films 6703 a and 6703 b areformed over the substrate 6701 (FIG. 68A). An amorphous semiconductorfilm is formed using a material containing silicon (Si) (such asSi_(x)Ge_(1-x)) as its main component or the like, by using a knownmethod (such as a sputtering method, an LPCVD method, or a plasma CVDmethod) over the insulating film 6702, which is formed in advance overthe substrate 6701; the amorphous semiconductor film is crystallized;and the semiconductor film is selectively etched; thus, theisland-shaped semiconductor films 6703 a and 6703 b can be provided.Note that crystallization of the amorphous semiconductor film can beperformed by a crystallization method such as a laser crystallizationmethod, a thermal crystallization method using RTA or an annealingfurnace, a thermal crystallization method using a metal element whichpromotes crystallization, or a combination thereof. Note that in FIGS.68A to 68D, end portions of the island-shaped semiconductor films 6703 aand 6703 b are provided to have an angle of about 90 degrees (θ=85 to100 degrees).

Next, the semiconductor films 6703 a and 6703 b are oxidized or nitridedby plasma treatment, so that semiconductor oxide films or semiconductornitride films 6721 a and 6721 b are formed on surfaces of thesemiconductor films 6703 a and 6703 b, respectively (FIG. 68B). Forexample, when Si is used for the semiconductor films 6703 a and 6703 b,silicon oxide (SiOx) or silicon nitride (SiNx) is formed as theinsulating film 6721 a and the insulating film 6721 b. Alternatively,the semiconductor films 6703 a and 6703 b may be oxidized by plasmatreatment and then may be nitrided by performing plasma treatment again.In this case, silicon oxide (SiOx) is formed in contact with thesemiconductor films 6703 a and 6703 b, and silicon nitride oxide SiNxOy)(x>y) is formed on the surface of the silicon oxide. Note that when thesemiconductor film is oxidized by plasma treatment, the plasma treatmentis performed in an oxygen atmosphere (e.g., in an atmosphere of oxygen(O₂) and an inert gas (including at least one of He, Ne, Ar, Kr, andXe), in an atmosphere of oxygen, hydrogen (H₂), and an inert gas, or inan atmosphere of dinitrogen monoxide and an inert gas). On the otherhand, when the semiconductor film is nitrided by plasma treatment, theplasma treatment is performed in a nitrogen atmosphere (e.g., in anatmosphere of nitrogen (N₂) and an inert gas (including at least one ofHe, Ne, Ar, Kr, and Xe), in an atmosphere of nitrogen, hydrogen, and aninert gas, or in an atmosphere of NH₃ and an inert gas). As an inertgas, Ar may be used, for example. Further, a gas mixture of Ar and Krmay be used as well. Therefore, the insulating films 6721 a and 6721 bcontain an inert gas (including as least one of He, Ne, Ar, Kr, and Xe)used for plasma treatment. When Ar is used, the insulating films 6721 aand 6721 b contain Ar.

In addition, the plasma treatment is performed in the atmospherecontaining the aforementioned gas, with conditions of an electrondensity ranging from 1×10¹¹ to 1×10¹³ cm⁻³ and a plasma electrontemperature ranging from 0.5 to 1.5 eV. Since the plasma electrondensity is high and the electron temperature in the vicinity of anobject to be treated (here, the semiconductor films 6703 a and 6703 b)formed over the substrate 6701 is low, damage by plasma to the object tobe treated can be prevented. Further, since the plasma electron densityis high at 1×10¹¹ cm⁻³ or more, an oxide film or a nitride film formedby oxidizing or nitriding the object to be treated by plasma treatmentis superior in its uniformity of thickness and the like as well as beingdense, as compared with a film formed by a CVD method, a sputteringmethod, or the like. Further, since the plasma electron temperature islow at 1 eV or less, oxidation or nitridation can be performed at alower temperature as compared with a conventional plasma treatment orthermal oxidation. For example, oxidation or nitridation can beperformed sufficiently even when plasma treatment is performed at atemperature lower than a strain point of a glass substrate by 100degrees or more. Note that for frequency for generating plasma, highfrequency waves such as microwaves (2.45 GHz) can be used. Note thathereinafter, the plasma treatment is performed using the aforementionedconditions unless otherwise specified.

Next, the gate insulating film 6704 is formed to cover the insulatingfilms 6721 a and 6721 b (FIG. 68C). The gate insulating film 6704 can beformed by a known method (such as a sputtering method, an LPCVD method,or a plasma CVD method) and provided with a single-layer structure or astacked-layer structure of an insulating film containing oxygen ornitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), siliconoxynitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y). Forexample, when Si is used for the semiconductor films 6703 a and 6703 band Si is oxidized by plasma treatment to form silicon oxide as theinsulating films 6721 a and 6721 b on the surfaces of the semiconductorfilms 6703 a and 6703 b, silicon oxide (SiOx) is formed as the gateinsulating film over the insulating films 6721 a and 6721 b.Alternatively, in FIG. 68B, when the insulating films 6721 a and 6721 bwhich are formed by oxidizing or nitriding the semiconductor films 6703a and 6703 b by plasma treatment are sufficiently thick, the insulatingfilms 6721 a and 6721 b can be used as gate insulating films.

Next, the gate electrode 6705 and the like are formed over the gateinsulating film 6704, so that a semiconductor device including then-channel transistor 6710 a and the p-channel transistor 6710 b whichuse the island-shaped semiconductor films 6703 a and 6703 b as channelregions can be manufactured (FIG. 68D).

In this manner, the surfaces of the semiconductor films 6703 a and 6703b are oxidized or nitrided by plasma treatment before the gateinsulating film 6704 is provided over the semiconductor films 6703 a and6703 b; thus, short circuits between the gate electrode and thesemiconductor films, which may be caused by a coverage defect of thegate insulating film 6704 at end portions 6751 a and 6751 b of thechannel regions, or the like can be prevented. That is, when the endportions of the island-shaped semiconductor films have an angle of about90 degrees (θ=85 to 100 degrees), the edges of the semiconductor filmsmight not be properly covered with a gate insulating film when the gateinsulating film is formed to cover the semiconductor film by a CVDmethod, a sputtering method, or the like. However, such a coveragedefect and the like of the gate insulating film at the edges of thesemiconductor films can be prevented by oxidizing or nitriding thesurfaces of the semiconductor films by plasma treatment in advance.

Alternatively, in FIGS. 68A to 68D, plasma treatment may be performedafter the gate insulating film 6704 is formed, whereby the gateinsulating film 6704 is oxidized or nitrided. In this case, plasmatreatment is performed on the gate insulating film 6704 (FIG. 69A),which is formed to cover the semiconductor films 6703 a and 6703 b, andthe gate insulating film 6704 is oxidized or nitrided, whereby aninsulating film 6723 which is an insulating oxide film or an insulatingnitride film is formed on the surface of the gate insulating film 6704(FIG. 69B). The plasma treatment can be performed under similarconditions to those in FIG. 68B. In addition, the insulating film 6723contains an inert gas which is used for the plasma treatment, and forexample, includes Ar when Ar is used for the plasma treatment.

Alternatively, in FIG. 69B, after the gate insulating film 6704 isoxidized by performing plasma treatment in an oxygen atmosphere once,plasma treatment may be performed again in a nitrogen atmosphere tonitride the gate insulating film 6704. In this case, silicon oxide(SiOx) or silicon oxynitride (SiOxNy) (x>y) is formed on the side onwhich semiconductor films 6703 a and 6703 b are, and silicon nitrideoxide (SiNxOy) (x>y) is formed to be in contact with the gate electrode6705. Thereafter, the gate electrode 6705 and the like are formed overthe gate insulating film 6704, whereby a semiconductor device includingthe n-channel transistor 6710 a and the p-channel transistor 6710 bwhich have the island-shaped semiconductor films 6703 a and 6703 b usedas channel regions can be manufactured (FIG. 69C). In this manner, whenplasma treatment is performed on the gate insulating film, the surfaceof the gate insulating film can be modified to form a dense film byoxidizing or nitriding the surface of the gate insulating film. Theinsulating film obtained by plasma treatment is denser and has fewerdefects such as a pinhole, as compared with an insulating film formed bya CVD method or a sputtering method. Thus, characteristics of thetransistors can be improved.

Note that FIGS. 69A to 69C show the case where the surfaces of thesemiconductor films 6703 a and 6703 b are oxidized or nitrided byperforming plasma treatment on the semiconductor films 6703 a and 6703 bin advance; however, a method may also be applied in which plasmatreatment is not performed on the semiconductor films 6703 a and 6703 bbut performed after the gate insulating film 6704 is formed. In thismanner, by performing plasma treatment before formation of the gateelectrode, an exposed portion of the semiconductor film due to acoverage defect can be oxidized or nitrided even if a coverage defectsuch as breaking of a gate insulating film is caused at end portions ofthe semiconductor film; thus, short circuits between the gate electrodeand the semiconductor film, which may be caused by a coverage defect ofthe gate insulating film at the edges of the semiconductor film, or thelike can be prevented.

In this manner, even when the island-shaped semiconductor films areformed to have edges at an angle of about 90 degrees, a short circuitbetween the gate electrodes and the semiconductor films, which arecaused by a coverage defect of the gate insulating film at the edges ofthe semiconductor films, or the like can be prevented by oxidizing ornitriding the semiconductor films or the gate insulating film by plasmatreatment.

Next, a case is shown in which the island-shaped semiconductor filmprovided over the substrate has an end portion with a tapered shape(0=30 to 85 degrees).

First, the island-shaped semiconductor films 6703 a and 6703 b areformed over the substrate 6701 (FIG. 70A). An amorphous semiconductorfilm is formed using a material containing silicon (Si) (such asSi_(x)Ge_(1-x)) as its main component or the like, using a known method(such as a sputtering method, an LPCVD method, or a plasma CVD method)over the insulating film 6702, which is formed in advance over thesubstrate 6701; the amorphous semiconductor film is crystallized by aknown crystallization method such as a laser crystallization method, athermal crystallization method using RTA or an annealing furnace, or athermal crystallization method using a metal element which promotescrystallization; and the semiconductor film is selectively etched andremoved; thus, the island-shaped semiconductor films 6703 a and 6703 bcan be provided. Note that in FIGS. 70A to 70D, the end portions of theisland-shaped semiconductor films 6703 a and 6703 b are provided to havea tapered shape (θ=30 to 85 degrees).

Next, the gate insulating film 6704 is formed to cover the semiconductorfilms 6703 a and 6703 b (FIG. 70B). The gate insulating film 6704 can beprovided to have a single-layer structure or a stacked-layer structureof an insulating film containing oxygen or nitrogen, such as siliconoxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y),or silicon nitride oxide (SiNxOy) (x>y), by a known method (such as asputtering method, an LPCVD method, or a plasma CVD method).

Next, the gate insulating film 6704 is oxidized or nitrided by plasmatreatment, so that an insulating film 6724 which is an insulating oxidefilm or an insulating nitride film is formed on the surface of the gateinsulating film 6704 (FIG. 70C). The plasma treatment can be performedunder similar conditions to the aforementioned description. For example,when silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) is usedas the gate insulating film 6704, the gate insulating film 6704 isoxidized by performing plasma treatment in an oxygen atmosphere, wherebya dense insulating film with few defects, such as a pinhole, can beformed on the surface of the gate insulating film as compared with agate insulating film formed by a CVD method, a sputtering method, or thelike. On the other hand, when the gate insulating film 6704 is nitridedby plasma treatment in a nitrogen atmosphere, silicon nitride oxide(SiNxOy) (x>y) can be provided as the insulating film 6724 on thesurface of the gate insulating film 6704. Alternatively, after the gateinsulating film 6704 is oxidized by performing plasma treatment in anoxygen atmosphere once, plasma treatment may be performed again in anitrogen atmosphere to nitride the gate insulating film 6704. Further,the insulating film 6724 contains an inert gas used for the plasmatreatment, and for example, contains Ar when Ar is used.

Next, the gate electrode 6705 and the like are formed over the gateinsulating film 6704, whereby a semiconductor device including then-channel transistor 6710 a and the p-channel transistor 6710 b whichhave the island-shaped semiconductor films 6703 a and 6703 b used aschannel regions can be manufactured (FIG. 70D).

In this manner, by performing plasma treatment on the gate insulatingfilm, the insulating film formed of an oxide film or a nitride film canbe provided on the surface of the gate insulating film; and the surfaceof the gate insulating film can be modified. The insulating filmobtained by oxidation or nitridation with plasma treatment is denser andhas fewer defects, such as a pinhole, as compared with a gate insulatingfilm formed by a CVD method or a sputtering method; therefore, thecharacteristics of the transistors can be improved. In addition, sinceshort circuits between the gate electrodes and the semiconductor films,which are caused by a coverage defect of the gate insulating film at theedges of the semiconductor films, or the like can be suppressed byforming the semiconductor films to have a tapered shape, short circuitsor the like between the gate electrodes and the semiconductor films canbe prevented more effectively by performing plasma treatment after thegate insulating film is formed.

Next, a manufacturing method of a semiconductor device which isdifferent from that in FIGS. 70A to 70D is described with reference todrawings. Specifically, a case is shown where plasma treatment isselectively performed on an end portion of a semiconductor film having atapered shape.

First, the island-shaped semiconductor films 6703 a and 6703 b areformed over the substrate 6701 (FIG. 71A). An amorphous semiconductorfilm is formed using a material containing silicon (Si) (such asSi_(x)Ge_(1-x)) as its main component or the like, using a known method(such as a sputtering method, an LPCVD method, or a plasma CVD method),over the insulating film 6702, which is formed in advance over thesubstrate 6701; the amorphous semiconductor film is crystallized; andthe semiconductor film is selectively etched using resists 6725 a and6725 b as masks; thus, the island-shaped semiconductor films 6703 a and6703 b can be provided. Note that crystallization of the amorphoussemiconductor film can be performed by a known method such as a lasercrystallization method, a thermal crystallization method using RTA or anannealing furnace, a thermal crystallization method using metal elementswhich promote crystallization, or a combination thereof.

Next, the end portions of the island-shaped semiconductor films 6703 aand 6703 b are selectively oxidized or nitrided by plasma treatmentbefore the resists 6725 a and 6725 b which are used for etching thesemiconductor films are removed, whereby an insulating film 6726 whichis a semiconductor oxide film or a semiconductor nitride film is formedin each end portion of the semiconductor films 6703 a and 6703 b (FIG.71B). The plasma treatment is performed under the aforementionedconditions. In addition, the insulating film 6726 contains an inert gasused for the plasma treatment.

Next, the gate insulating film 6704 is formed to cover the semiconductorfilms 6703 a and 6703 b (FIG. 71C). The gate insulating film 6704 can beformed in a similar manner to the above description.

Next, the gate electrodes 6705 and the like are formed over the gateinsulating film 6704, whereby a semiconductor device including then-channel transistor 6710 a and the p-channel transistor 6710 b whichhave the island-shaped semiconductor films 6703 a and 6703 b used aschannel regions can be manufactured (FIG. 71D).

When the end portions of the semiconductor films 6703 a and 6703 b havetapered shapes, end portions 6752 a and 6752 b of the channel regions,which are formed in a part of the semiconductor films 6703 a and 6703 b,are also tapered, and the thickness of the semiconductor films and thegate insulating film in that portion are different from that in acentral portion, which may adversely affect the characteristics of thetransistors. Here, insulating films are formed in the end portions ofthe semiconductor films, which are formed by selectively oxidizing ornitriding the end portions of the channel regions by plasma treatment;thus, such an effect on the transistors due to the end portions of thechannel regions can be reduced.

Although FIGS. 71A to 71D show an example where only the end portions ofthe semiconductor films 6703 a and 6703 b are oxidized or nitrided byplasma treatment, the gate insulating film 6704 can also be oxidized ornitrided by plasma treatment as shown in FIGS. 70A to 70D (FIG. 73A).

Next, a manufacturing method of a semiconductor device which isdifferent from the aforementioned manufacturing method is described withreference to drawings. Specifically, a case is shown where plasmatreatment is performed on semiconductor films with tapered shapes.

First, the island-shaped semiconductor films 6703 a and 6703 b areformed over the substrate 6701 in a similar manner to the abovedescription (FIG. 72A).

Next, the semiconductor films 6703 a and 6703 b are oxidized or nitridedby plasma treatment, whereby insulating films 6727 a and 6727 b whichare semiconductor oxide films or semiconductor nitride films are formedon the surfaces of the semiconductor films 6703 a and 6703 b,respectively (FIG. 72B). The plasma treatment can be performed in amanner similar to that performed under the aforementioned conditions.For example, when Si is used for the semiconductor films 6703 a and 6703b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as theinsulating films 6727 a and 6727 b. In addition, after the semiconductorfilms 6703 a and 6703 b are oxidized by plasma treatment, plasmatreatment may be performed again on the semiconductor films 6703 a and6703 b to nitride the semiconductor films 6703 a and 6703 b. In thiscase, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) isformed in contact with the semiconductor films 6703 a and 6703 b, andsilicon nitride oxide (SiNxOy) (x>y) is formed on the surface of thesilicon oxide. Therefore, the insulating films 6727 a and 6727 b containan inert gas used for the plasma treatment. Note that the end portionsof the semiconductor films 6703 a and 6703 b are simultaneously oxidizedor nitrided by performing plasma treatment.

Next, the gate insulating film 6704 is formed to cover the insulatingfilms 6727 a and 6727 b (FIG. 72C). The gate insulating film 6704 can beformed to have a single-layer structure or a stacked-layer structure ofan insulating film containing oxygen or nitrogen, such as silicon oxide(SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), orsilicon nitride oxide (SiNxOy) (x>y), by a known method (such as asputtering method, an LPCVD method, or a plasma CVD method). Forexample, when Si is used for the semiconductor films 6703 a and 6703 band the surfaces of the semiconductor films 6703 a and 6703 b areoxidized by plasma treatment to form silicon oxide as the insulatingfilms 6727 a and 6727 b, silicon oxide (SiOx) is formed as a gateinsulating film over the insulating films 6727 a and 6727 b.

Next, the gate electrodes 6705 and the like are formed over the gateinsulating film 6704, whereby a semiconductor device including then-channel transistor 6710 a and the p-channel transistor 6710 b whichhave the island-shaped semiconductor films 6703 a and 6703 b used aschannel regions can be manufactured (FIG. 72D).

When the end portions of the semiconductor films have tapered shape, endportions 6753 a and 6753 b of the channel regions, which are formed in apart of the semiconductor films, are also tapered, which may adverselyaffect characteristics of semiconductor elements. When semiconductorfilms are oxidized or nitrided by plasma treatment, the end portions ofthe channel regions are also oxidized or nitrided; thus, such an effecton the semiconductor elements can be reduced.

Although FIGS. 72A to 72D show an example where only the semiconductorfilms 6703 a and 6703 b are oxidized or nitrided by plasma treatment,the gate insulating film 6704 can also be oxidized or nitrided by plasmatreatment as shown in FIGS. 70A to 70D (FIG. 73B). In this case, afterthe gate insulating film 6704 is oxidized by plasma treatment in anoxygen atmosphere once, plasma treatment may be performed again in anitrogen atmosphere to nitride the gate insulating film 6704. In thiscase, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) isformed on the side on which the semiconductor films 6703 a and 6703 bare, and silicon nitride oxide (SiNxOy) (x>y) is formed to be in contactwith the gate electrodes 6705.

As described above, the surface of the semiconductor film or the gateinsulating film is modified by oxidizing or nitriding the semiconductorfilm or the gate insulating film by plasma treatment, so that a denseinsulating film with good film quality can be formed. As a result, evenwhen the insulating film is formed to be thinner, a defect such as apinhole can be prevented, and miniaturization and higher performance ofa semiconductor element such as a transistor can be realized.

This embodiment mode shows an example where plasma treatment isperformed to oxide or nitride the semiconductor films 6703 a and 6703 bor the gate insulating film 6704 shown in FIGS. 67A to 67C; however, alayer to be oxidized or nitrided by plasma treatment is not limitedthereto. For example, plasma treatment may be performed on the substrate6701 or the insulating film 6702, or on the insulating film 6706 or theinsulating film 6707.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 7.

Embodiment Mode 9

In this embodiment mode, hardware controlling the driving method shownin Embodiment Modes 1 to 6 is described.

FIG. 74 shows a general block diagram. A pixel portion 7404, a signalline driver circuit 7406, and a scan line driver circuit 7405 areprovided over a substrate 7401. Further, a power supply circuit, aprecharge circuit, a timing generating circuit, and the like may also beprovided. Note that the signal line driver circuit 7406 and the scanline driver circuit 7405 need not be provided if not necessary. In thiscase, a circuit which is not provided over the substrate may be formedinto an IC. The IC may be provided over the substrate 7401 by COG (ChipOn Glass). Alternatively, the IC may be provided over a connectionsubstrate 7407 which connects a peripheral circuit substrate 7402 andthe substrate 7401.

Signal 7403 are input to the peripheral circuit substrate 7402. Then, bycontrol of a controller 7408, the signals are stored in memories 7409and 7410, and the like. When the signals 7403 are analog signals, it isoften converted from analog to digital to be stored in the memories 7409and 7410 and the like. Then, the controller 7408 outputs a signal to thesubstrate 7401 by using the signals stored in the memories 7409 and 7410and the like.

In order to realize the driving method shown in Embodiment Modes 1 to 6,the controller 7408 controls the order of appearance of subframes andthe like to output the signal to the substrate 7401.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 8.

Embodiment Mode 10

In this embodiment mode, structure examples of an EL module and an ELtelevision receiver using a display device of the invention aredescribed.

FIG. 75 shows an EL module in which a display panel 7501 and a circuitboard 7502 are combined. The display panel 7501 includes a pixel portion7503, a scan line driver circuit 7504, and a signal line driver circuit7505. For example, a control circuit 7506, a signal dividing circuit7507, and the like are formed over the circuit board 7502. The displaypanel 7501 and the circuit board 7502 are connected to each other by aconnection wiring 7508. As the connection wiring, an FPC or the like canbe used.

The control circuit 7506 corresponds to the controller 7408, the memory7409, the memory 7410, or the like in Embodiment Mode 9. The order ofappearance of subframes and the like is controlled mainly by the controlcircuit 7506.

In the display panel 7501, the pixel portion and a part of peripheraldriver circuits (a driver circuit having a low operation frequency amonga plurality of driver circuits) may be formed over a substrate by usingtransistors in an integrated manner, and another part of the peripheraldriver circuits (a driver circuit having a high operation frequencyamong the plurality of driver circuits) may be formed over an IC chip.The IC chip may be mounted on the display panel 7501 by COG (Chip OnGlass) or the like. Alternatively, the IC chip may be mounted on thedisplay panel 7501 by using TAB (Tape Automated Bonding) or a printedwiring board.

In addition, by impedance conversion of a signal set to a scan line or asignal line by a buffer circuit, the length of a writing period forpixels of each row can be reduced. Thus, a high-definition displaydevice can be provided.

Moreover, in order to further reduce power consumption, a pixel portionmay be formed over a glass substrate by using transistors, and allsignal line driver circuits may be formed over an IC chip, which may bemounted on a display panel by COG (Chip On Glass) or the like.

For example, the entire screen of the display panel may be divided intoseveral regions, and an IC chip in which a part or all of the peripheraldriver circuits (the signal line driver circuit, the scan line drivercircuit, and the like) are formed may be arranged in each region to bemounted on the display panel by COG (Chip On Glass) or the like. FIG. 76shows a structure of the display panel in this case.

FIG. 76 shows an example where driving is performed by dividing theentire screen into four regions and using eight IC chips. A displaypanel includes a substrate 7610, a pixel portion 7611, FPCs 7612 a to7612 h, and IC chips 7613 a to 7613 h. Among the eight IC chips, asignal line driver circuit is fowled using the IC chips 7613 a to 7613d, and a scan line driver circuit is formed using the IC chips 7613 e to7613 h. It becomes possible to drive only an arbitrary screen region ofthe four screen regions by driving arbitrary IC chips. For example, whenonly the IC chips 7613 a and 7613 e are driven, only the upper leftregion of the four screen regions can be driven. Thus, power consumptioncan be reduced.

FIG. 77 shows an example of a display device having a differentstructure. A display panel of FIG. 77 includes a pixel portion 7721 inwhich a plurality of pixels 7730 is arranged, a scan line driver circuit7722 which controls a signal of a scan line 7733, and a signal linedriver circuit 7723 which controls a signal of a signal line 7731, overa substrate 7720. In addition, a monitor circuit 7724 for correctingchanges in the luminance of a light emitting element included in thepixel 7730 may also be provided. The light emitting element included inthe pixel 7730 and a light emitting element included in the monitorcircuit 7724 have the same structure. The light emitting element has astructure where a layer including a material which exhibitselectroluminescence is interposed between a pair of electrodes.

The peripheral portion of the substrate 7720 includes an input terminal7725 which inputs a signal from an external circuit to the scan linedriver circuit 772, an input terminal 7726 which inputs a signal from anexternal circuit to the signal line driver circuit 7723, and an inputterminal 7729 which inputs a signal to the monitor circuit 7724.

In order to make the light emitting element included in the pixel 7730emit light, power is necessary to be supplied from an external circuit.A power supply line 7732 provided in the pixel portion 7721 is connectedto an external circuit through an input terminal 7727. Resistance lossoccurs in the power supply line 7732 due to the length of a lead wiring;thus, a plurality of input terminals 7727 is preferably provided in theperipheral portion of the substrate 7720. The input terminals 7727 areprovided on opposite sides of the substrate 7720 and arranged so thatluminance unevenness is inconspicuous at the surface of the pixelportion 7721. In other words, display in which one side of the screenlights up while the opposite side remains dark is prevented fromoccurring. In addition, an electrode, which is one of a pair ofelectrodes included in the light emitting element, on the opposite sideof the electrode connected to the power supply line 7732 is formed as acommon electrode which is shared among the plurality of pixels 7730.Further, a plurality of terminals 7728 is provided to reduce resistanceloss in the electrode.

In such a display panel, a power supply line is formed using a lowresistance material such as Cu, which is especially effective when ascreen size is increased. For example, when a screen size is a 13-inchclass, the length of a diagonal line is 340 mm, while 1500 mm or morefor a 60-inch class. In such a case, since wiring resistance cannot beignored, it is preferable to use a low resistance material such as Cufor a wiring. In addition, in consideration of wiring delay, a signalline or a scan line may be formed in a similar manner.

With such an EL module provided with the panel structure as describedabove, an EL television receiver can be completed. FIG. 78 is a blockdiagram showing the main structure of an EL television receiver. A tuner7801 receives video signals and audio signals. The video signals areprocessed by a video signal amplifier circuit 7802; a video signalprocessing circuit 7803 for converting a signal output from the videosignal amplifier circuit 7802 into a color signal corresponding to eachcolor of red, green, and blue; and the control circuit 7506 forconverting the video signal to be input to a driver circuit. The controlcircuit 7506 outputs signals to each of the scan line and the signalline. When digital drive is performed, the signal dividing circuit 7507may be provided on the signal line side to divide an input digitalsignal into M signals before the signals are supplied.

Among the signals received by the tuner 7801, the audio signals aretransmitted to an audio signal amplifier circuit 7804, and an outputthereof is supplied to a speaker 7806 through an audio signal processingcircuit 7805. A control circuit 7807 receives control data on areceiving station (reception frequency) or sound volume from an inputportion 7808 and transmits signals to the tuner 7801 and the audiosignal processing circuit 7805.

By incorporating the EL module into a housing, a television receiver canbe completed. A display portion is formed using such an EL module. Inaddition, a speaker, a video input terminal, and the like are providedas appropriate.

It is needless to say that the invention is not limited to thetelevision receiver and can be applied to various uses, especially as alarge display medium such as a monitor of a personal computer, aninformation display board at a train station, airport, or the like, oran advertisement display board on the street.

By using a display device and a driving method thereof according to theinvention, a clear image can be displayed with reduced pseudo contour.

Note that the content described in this embodiment mode can be freelyimplemented in combination with the content described in EmbodimentModes 1 to 9.

Embodiment Mode 11

Electronic appliances using the display device of the invention includecameras such as a video camera and a digital camera, a goggle-typedisplay (head mounted display), a navigation system, an audioreproducing device (such as a car audio and an audio component), anotebook computer, a game machine, a portable information terminal (suchas a mobile computer, a cellular phone, a mobile game machine, and anelectronic book), an image reproducing device provided with a recordingmedium (specifically, a device for reproducing a recording medium suchas a digital versatile disc (DVD) and having a display for displayingthe reproduced image) and the like. FIGS. 79A to 79H show specificexamples of these electronic appliances.

FIG. 79A shows a self-light emitting display, which includes a housing7901, a supporting base 7902, a display portion 7903, speaker portions7904, a video input terminal 7905, and the like. The invention can beused for a display device forming the display portion 7903. According tothe invention, a clear image can be displayed with reduced pseudocontour. A backlight is not necessary since the display is a self-lightemitting type, and the display portion can be made to be thinner thanthat of a liquid crystal display. Note that a display includes alldisplay devices for information display, such as display devices for apersonal computer, for TV broadcast reception, and for displays ofadvertisements.

FIG. 79B shows a digital still camera, which includes a main body 7906,a display portion 7907, an image receiving portion 7908, operation keys7909, an external connection port 7910, a shutter button 7911, and thelike. The invention can be used for a display device forming the displayportion 7907. According to the invention, a clear image can be displayedwith reduced pseudo contour.

FIG. 79C shows a notebook computer, which includes a main body 7912, ahousing 7913, a display portion 7914, a keyboard 7915, an externalconnection port 7916, a pointing device 7917, and the like. Theinvention can be used for a display device forming the display portion7914. According to the invention, a clear image can be displayed withreduced pseudo contour.

FIG. 79D shows a mobile computer, which includes a main body 7918, adisplay portion 7919, a switch 7920, operation keys 7921, an infraredport 7922, and the like. The invention can be used for a display deviceforming the display portion 7919. According to the invention, a clearimage can be displayed with reduced pseudo contour.

FIG. 79E shows an image reproducing device provided with a recordingmedium reading portion (specifically, a DVD reproducing device, forexample), which includes a main body 7923, a housing 7924, a displayportion A 7925, a display portion B 7926, a recording medium (such asDVD) reading portion 7927, an operation key 7928, a speaker portion7929, and the like. The display portion A 7925 mainly displays imageinformation, and the display portion B 7926 mainly displays textinformation. The invention can be used for a display device forming thedisplay portion A 7925 and the display portion B 7926. According to theinvention, a clear image can be displayed with reduced pseudo contour.

FIG. 79F shows a goggle-type display (head mounted display), whichincludes a main body 7930, a display portion 7931, an arm portion 7932,and the like. The invention can be used for a display device forming thedisplay portion 7931. According to the invention, a clear image can bedisplayed with reduced pseudo contour.

FIG. 796 shows a video camera, which includes a main body 7933, adisplay portion 7934, a housing 7935, an external connection port 7936,a remote control receiving portion 7937, an image receiving portion7938, a battery 7939, an audio input portion 7940, operation keys 7941,and the like. The invention can be used for a display device foaming thedisplay portion 7934. According to the invention, a clear image can bedisplayed with reduced pseudo contour.

FIG. 79H shows a cellular phone, which includes a main body 7942, ahousing 7943, a display portion 7944, an audio input portion 7945, anaudio output portion 7946, operation keys 7947, an external connectionport 7948, an antenna 7949, and the like. The invention can be used fora display device foiining the display portion 7944. According to theinvention, a clear image can be displayed with reduced pseudo contour.

Note that when a light emitting material with high luminance is used,the invention can be applied to a front or rear projector which projectsand magnifies light including output image information with a lens orthe like.

Moreover, in recent years, the above electronic appliances have oftenbeen used for displaying information distributed through electroniccommunication lines such as the Internet or CATV (Cable TV), and inparticular, opportunity to display moving image information has beenincreased. Since a light emitting material has extremely high responsespeed, a light emitting device is suitable for displaying moving images.

Since a light emitting display device consumes power in its lightemitting portion, it is preferable to display information by utilizingas small a light emitting portion as possible. Accordingly, when a lightemitting display device is used for a display portion of a portableinformation terminal which mainly displays text information, such as acellular phone and an audio reproducing device in particular, it ispreferable to drive the light emitting display device in such a mannerthat text information is displayed with a light emitting portion whileusing a non-light emitting portion as a background.

As described above, the application range of the invention is so widethat the invention can be applied to electronic appliances of variousfields. Further, an electronic appliance of this embodiment mode can usethe display device having any structure shown in Embodiment Modes 1 to10.

This application is based on Japanese Patent Application serial No.2006-151100 filed in Japan Patent Office on May 31, 2006, the entirecontents of which are hereby incorporated by reference.

1. A semiconductor device comprising: a plurality of pixels over asubstrate, wherein at least one pixel of the plurality of pixelscomprises: a first subpixel, wherein the first subpixel comprises: afirst transistor that comprises an oxide semiconductor comprisingindium; and a first pixel electrode electrically connected to the firsttransistor; a second subpixel, wherein the second subpixel comprises: asecond transistor that comprises an oxide semiconductor comprisingindium; a second pixel electrode electrically connected to the secondtransistor; and a display medium over the substrate, the display mediumcomprising an electronic ink, wherein one image of at least one of theplurality of pixels is displayed by a plurality of signals.
 2. Thesemiconductor device according to claim 1, wherein the semiconductordevice is an electronic paper.
 3. The semiconductor device according toclaim 1, wherein the substrate over which the first transistor thatcomprises the oxide semiconductor comprising indium and the secondtransistor that comprises the oxide semiconductor comprising indium areprovided is a plastic substrate.
 4. The semiconductor device accordingto claim 1, wherein each of the first subpixel and the second subpixelcomprises first to m-th subpixel, wherein an area of the (s+1)thsubpixel is twice an area of the s-th subpixel, wherein one frame ofeach of the first to m-th subpixels is divided into first to n-thsubframes, wherein a display period of the (p+1)th subframe is 2^(m)times longer than a display period of a p-th subframe, wherein at leastone of the first to n-th subframes is divided into a plurality ofsubframes each having a display period shorter than that of the one ofthe first to n-th subframes, so that the first to n-th subframes areincreased to first to t-th subframes, wherein when at least one of thefirst to m-th subpixels is displayed in at least one of the first tot-th subframes for displaying a gray scale level of i, the one of thefirst to m-th subpixels is displayed in the one of the first to t-thsubframes for whenever displaying a gray scale level larger than i,wherein one gate selection period is divided into two subgate selectionperiods, wherein m is an integer of m≧2, wherein s is an integer of1≦s≦(m−1), wherein n is an integer of n≧2, wherein p is an integer of1≦p≦(n−1), wherein t is an integer of t>n, and wherein i is an integerof i≧0.
 5. The semiconductor device according to claim 1, furthercomprising at least one of a power supply circuit, a flexible printedcircuit, a printed wiring board, and a circuit board.
 6. Thesemiconductor device according to claim 1, wherein at least one of theoxide semiconductor comprised in the first transistor and the oxidesemiconductor comprised in the second transistor is InGaZnO.
 7. Thesemiconductor device according to claim 1, wherein at least one pixel ofthe plurality of pixels comprises a first pixel capable of displaying ared color, a second pixel capable of displaying a green color, and athird pixel capable of displaying a blue color, wherein an area of thefirst subpixel and an area of the second subpixel is different from eachother, and wherein an area of the first pixel, an area of the secondpixel, and an area of the third pixel are different from one another. 8.A semiconductor device comprising: a plurality of pixels over asubstrate, wherein at least one pixel of the plurality of pixelscomprises: a first subpixel, wherein the first subpixel comprises: afirst transistor that comprises an oxide semiconductor comprisingindium; and a first pixel electrode electrically connected to the firsttransistor; a second subpixel, wherein the second subpixel comprises: asecond transistor that comprises an oxide semiconductor comprisingindium; a second pixel electrode electrically connected to the secondtransistor; and a display medium over the substrate, the display mediumcomprising an electronic ink, a common electrode that faces to the firstpixel electrode and the second pixel electrode; a terminal provided onthe substrate, the terminal being electrically connected to the commonelectrode, wherein one image of at least one of the plurality of pixelsis displayed by a plurality of signals.
 9. The semiconductor deviceaccording to claim 8, wherein the semiconductor device is an electronicpaper.
 10. The semiconductor device according to claim 8, wherein thesubstrate over which the first transistor that comprises the oxidesemiconductor comprising indium and the second transistor that comprisesthe oxide semiconductor comprising indium are provided is a plasticsubstrate.
 11. The semiconductor device according to claim 8, whereineach of the first subpixel and the second subpixel comprises first tom-th subpixel, wherein an area of the (s+1)th subpixel is twice an areaof the s-th subpixel, wherein one frame of each of the first to m-thsubpixels is divided into first to n-th subframes, wherein a displayperiod of the (p+1)th subframe is 2^(m) times longer than a displayperiod of a p-th subframe, wherein at least one of the first to n-thsubframes is divided into a plurality of subframes each having a displayperiod shorter than that of the one of the first to n-th subframes, sothat the first to n-th subframes are increased to first to t-thsubframes, wherein when at least one of the first to m-th subpixels isdisplayed in at least one of the first to t-th subframes for displayinga gray scale level of i, the one of the first to m-th subpixels isdisplayed in the one of the first to t-th subframes for wheneverdisplaying a gray scale level larger than i, wherein one gate selectionperiod is divided into two subgate selection periods, wherein m is aninteger of m≧2, wherein s is an integer of 1≦s≦(m−1), wherein n is aninteger of n≧2, wherein p is an integer of 1≦p≦(n−1), wherein t is aninteger of t>n, and wherein i is an integer of i≧0.
 12. Thesemiconductor device according to claim 8, further comprising at leastone of a power supply circuit, a flexible printed circuit, a printedwiring board, and a circuit board.
 13. The semiconductor deviceaccording to claim 8, further comprising a second terminal on thesubstrate, wherein the second terminal is electrically connected to thecommon electrode.
 14. The semiconductor device according to claim 8,wherein at least one of the oxide semiconductor comprised in the firsttransistor and the oxide semiconductor comprised in the secondtransistor is InGaZnO.
 15. The semiconductor device according to claim8, wherein at least one pixel of the plurality of pixels comprises afirst pixel capable of displaying a red color, a second pixel capable ofdisplaying a green color, and a third pixel capable of displaying a bluecolor, wherein an area of the first subpixel and an area of the secondsubpixel is different from each other, and wherein an area of the firstpixel, an area of the second pixel, and an area of the third pixel aredifferent from one another.
 16. A semiconductor device comprising: aplurality of pixels over a substrate, wherein at least one pixel of theplurality of pixels comprises: a first subpixel, wherein the firstsubpixel comprises: a first transistor that comprises an oxidesemiconductor comprising indium; and a first pixel electrodeelectrically connected to the first transistor; a second subpixel,wherein the second subpixel comprises: a second transistor thatcomprises an oxide semiconductor comprising indium; a second pixelelectrode electrically connected to the second transistor; and a displaymedium over the substrate, the display medium comprising an electronicink, a common electrode that faces to the first pixel electrode and thesecond pixel electrode; a terminal provided on the substrate, theterminal being electrically connected to the common electrode, whereinone image of at least one of the plurality of pixels is displayed by aplurality of signals, and wherein an entirety of the terminal overlapswith the substrate.
 17. The semiconductor device according to claim 16,wherein the semiconductor device is an electronic paper.
 18. Thesemiconductor device according to claim 16, wherein the substrate overwhich the first transistor that comprises the oxide semiconductorcomprising indium and the second transistor that comprises the oxidesemiconductor comprising indium are provided is a plastic substrate. 19.The semiconductor device according to claim 16, wherein each of thefirst subpixel and the second subpixel comprises first to m-th subpixel,wherein an area of the (s+1)th subpixel is twice an area of the s-thsubpixel, wherein one frame of each of the first to m-th subpixels isdivided into first to n-th subframes, wherein a display period of the(p+1)th subframe is 2^(m) times longer than a display period of a p-thsubframe, wherein at least one of the first to n-th subframes is dividedinto a plurality of subframes each having a display period shorter thanthat of the one of the first to n-th subframes, so that the first ton-th subframes are increased to first to t-th subframes, wherein when atleast one of the first to m-th subpixels is displayed in at least one ofthe first to t-th subframes for displaying a gray scale level of i, theone of the first to m-th subpixels is displayed in the one of the firstto t-th subframes for whenever displaying a gray scale level larger thani, wherein one gate selection period is divided into two subgateselection periods, wherein m is an integer of m≧2, wherein s is aninteger of 1≦s≦(m−1), wherein n is an integer of n≧2, wherein p is aninteger of 1≦p≦(n−1), wherein t is an integer of t>n, and wherein i isan integer of i≧0.
 20. The semiconductor device according to claim 16,further comprising at least one of a power supply circuit, a flexibleprinted circuit, a printed wiring board, and a circuit board.
 21. Thesemiconductor device according to claim 16, further comprising a secondterminal on the substrate, wherein the second terminal is electricallyconnected to the common electrode.
 22. The semiconductor deviceaccording to claim 16, wherein at least one of the oxide semiconductorcomprised in the first transistor and the oxide semiconductor comprisedin the second transistor is InGaZnO.
 23. The semiconductor deviceaccording to claim 16, wherein at least one pixel of the plurality ofpixels comprises a first pixel capable of displaying a red color, asecond pixel capable of displaying a green color, and a third pixelcapable of displaying a blue color, wherein an area of the firstsubpixel and an area of the second subpixel is different from eachother, and wherein an area of the first pixel, an area of the secondpixel, and an area of the third pixel are different from one another.